Summary

 Design Name  CLR_SYT_FF
 Fitting Status  Successful
 Software Version  J.30
 Device Used  XC95108-10-PC84
 Date   5- 2-2010, 7:48AM

RESOURCES SUMMARY
Macrocells Used Pterms Used Registers Used Pins Used Function Block Inputs Used
2/108  (2%) 3/540  (1%) 2/108  (2%) 5/69  (8%) 2/216  (1%)

PIN RESOURCES
Signal Type Required Mapped
 Input  1  1
 Output  2  2
 Bidirectional  0  0
 GCK  1  1
 GTS  0  0
 GSR  1  1
Pin Type Used Total
 I/O  3  63
 GCK/IO  1  3
 GTS/IO  0  2
 GSR/IO  1  1

GLOBAL RESOURCES
 Signal mapped onto global clock net (GCK2)  CLK
 Signal mapped onto global output enable net (GSR)  CLR

POWER DATA
 Macrocells in high performance mode (MCHP)  2
 Macrocells in low power mode (MCLP)  0
 Total macrocells used (MC)  2