Equations

********** Mapped Logic **********
FDCPE_Q: FDCPE port map (Q,Q_D,CLK,'0','0');
     Q_D <= ((K AND Q_OBUF.LFBK)
      OR (NOT J AND NOT Q_OBUF.LFBK));
FDCPE_QB: FDCPE port map (QB,QB_D,CLK,'0','0');
     QB_D <= ((K AND Q_OBUF.LFBK)
      OR (NOT J AND NOT Q_OBUF.LFBK));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);