cpldfit: version J.30 Xilinx Inc. Fitter Report Design Name: TRA_LIGHT Date: 4-24-2010, 11:40AM Device Used: XC95108-10-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 75 /108 ( 69%) 206 /540 ( 38%) 104/216 ( 48%) 50 /108 ( 46%) 25 /69 ( 36%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 11/18 15/36 15 16/90 0/12 FB2 16/18 28/36 28 35/90 2/12 FB3 16/18 19/36 19 62/90 8/12 FB4 16/18 31/36 31 17/90 11/11* FB5 0/18 0/36 0 0/90 0/11 FB6 16/18 11/36 11 76/90 3/11 ----- ----- ----- ----- 75/108 104/216 206/540 24/69 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 0 0 | I/O : 24 63 Output : 24 24 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 25 25 ** Power Data ** There are 75 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 24 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State SEG<1> 2 2 FB2_2 71 I/O O STD FAST RESET SEG<0> 2 2 FB2_3 72 I/O O STD FAST RESET LED<7> 4 12 FB3_8 19 I/O O STD FAST RESET LED<6> 5 12 FB3_9 20 I/O O STD FAST RESET LED<5> 4 12 FB3_11 21 I/O O STD FAST RESET LED<4> 2 10 FB3_12 23 I/O O STD FAST RESET LED<3> 2 10 FB3_14 24 I/O O STD FAST RESET LED<2> 4 12 FB3_15 25 I/O O STD FAST RESET LED<1> 5 12 FB3_16 26 I/O O STD FAST RESET LED<0> 4 12 FB3_17 31 I/O O STD FAST RESET SEL<3> 0 0 FB4_2 57 I/O O STD FAST SEL<4> 0 0 FB4_3 58 I/O O STD FAST SEL<5> 0 0 FB4_5 61 I/O O STD FAST SEL<6> 1 2 FB4_6 62 I/O O STD FAST SEL<7> 1 2 FB4_8 63 I/O O STD FAST SEG<7> 0 0 FB4_9 65 I/O O STD FAST SEG<6> 2 2 FB4_11 66 I/O O STD FAST RESET SEG<5> 2 2 FB4_12 67 I/O O STD FAST RESET SEG<4> 2 2 FB4_14 68 I/O O STD FAST RESET SEG<3> 2 2 FB4_15 69 I/O O STD FAST RESET SEG<2> 2 5 FB4_17 70 I/O O STD FAST RESET SEL<0> 1 2 FB6_14 54 I/O O STD FAST SEL<1> 1 2 FB6_15 55 I/O O STD FAST SEL<2> 0 0 FB6_17 56 I/O O STD FAST ** 51 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State CNT<5> 1 5 FB1_8 STD RESET CNT<4> 1 4 FB1_9 STD RESET CNT<3> 1 3 FB1_10 STD RESET CNT<2> 1 2 FB1_11 STD RESET CNT<1> 1 1 FB1_12 STD RESET CNT<0> 0 0 FB1_13 STD RESET DIS_BUFF<3>/DIS_BUFF<3>_D2 2 3 FB1_14 STD DIS_BUFF<2>/DIS_BUFF<2>_D2 2 3 FB1_15 STD DIS_BUFF<1>/DIS_BUFF<1>_D2 2 3 FB1_16 STD $OpTx$FX_DC$46 2 3 FB1_17 STD TIME<1> 3 5 FB1_18 STD RESET SEC 1 24 FB2_5 STD RESET CNT<7> 1 7 FB2_6 STD RESET CNT<6> 1 6 FB2_7 STD RESET CNT<22> 1 22 FB2_8 STD RESET CNT<9> 2 24 FB2_9 STD RESET CNT<23> 2 24 FB2_10 STD RESET CNT<21> 2 24 FB2_11 STD RESET CNT<20> 2 24 FB2_12 STD RESET CNT<18> 2 24 FB2_13 STD RESET CNT<17> 2 24 FB2_14 STD RESET CNT<16> 2 24 FB2_15 STD RESET CNT<12> 2 24 FB2_16 STD RESET CNT<11> 2 24 FB2_17 STD RESET CNT<8> 9 24 FB2_18 STD RESET TIME<0> 2 11 FB3_3 STD RESET TIME<6> 3 9 FB3_4 STD RESET STATUS<1> 3 11 FB3_5 STD RESET STATUS<0> 3 11 FB3_6 STD RESET TIME<5> 5 11 FB3_7 STD RESET TIME<3> 5 9 FB3_10 STD RESET TIME<2> 5 11 FB3_13 STD RESET TIME<4> 6 11 FB3_18 STD RESET CNT<19> 1 19 FB4_7 STD RESET CNT<15> 1 15 FB4_10 STD RESET CNT<14> 1 14 FB4_13 STD RESET CNT<13> 1 13 FB4_16 STD RESET CNT<10> 1 10 FB4_18 STD RESET SEG_3/SEG_3_SETF 10 9 FB6_1 STD TIME<7> 2 9 FB6_3 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State SEG_6/SEG_6_RSTF 4 9 FB6_4 STD SEG_4/SEG_4_SETF 4 9 FB6_5 STD SEG_1/SEG_1_RSTF 4 9 FB6_6 STD SEG_0/SEG_0_RSTF 4 9 FB6_7 STD $OpTx$FX_DC$48 4 7 FB6_8 STD SEG_5/SEG_5_RSTF 6 9 FB6_9 STD SEG_3/SEG_3_RSTF 6 9 FB6_10 STD SEG_2/SEG_2_SETF__$INT 6 9 FB6_11 STD SEG_5/SEG_5_SETF 8 9 FB6_12 STD SEG_1/SEG_1_SETF 8 9 FB6_13 STD SEG_0/SEG_0_SETF 8 9 FB6_16 STD ** 1 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK FB1_12 9 GCK/I/O GCK Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 15/21 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O (unused) 0 0 0 5 FB1_3 2 I/O (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 3 I/O (unused) 0 0 0 5 FB1_6 4 I/O (unused) 0 0 0 5 FB1_7 (b) CNT<5> 1 0 0 4 FB1_8 5 I/O (b) CNT<4> 1 0 0 4 FB1_9 6 I/O (b) CNT<3> 1 0 0 4 FB1_10 (b) (b) CNT<2> 1 0 0 4 FB1_11 7 I/O (b) CNT<1> 1 0 0 4 FB1_12 9 GCK/I/O GCK CNT<0> 0 0 0 5 FB1_13 (b) (b) DIS_BUFF<3>/DIS_BUFF<3>_D2 2 0 0 3 FB1_14 10 GCK/I/O (b) DIS_BUFF<2>/DIS_BUFF<2>_D2 2 0 0 3 FB1_15 11 I/O (b) DIS_BUFF<1>/DIS_BUFF<1>_D2 2 0 0 3 FB1_16 12 GCK/I/O (b) $OpTx$FX_DC$46 2 0 0 3 FB1_17 13 I/O (b) TIME<1> 3 0 0 2 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: CNT<0>.LFBK 6: CNT<4>.LFBK 11: TIME<3> 2: CNT<12> 7: SEC 12: TIME<4> 3: CNT<1>.LFBK 8: TIME<0> 13: TIME<5> 4: CNT<2>.LFBK 9: TIME<1>.LFBK 14: TIME<6> 5: CNT<3>.LFBK 10: TIME<2> 15: TIME<7> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CNT<5> X.XXXX.................................. 5 5 CNT<4> X.XXX................................... 4 4 CNT<3> X.XX.................................... 3 3 CNT<2> X.X..................................... 2 2 CNT<1> X....................................... 1 1 CNT<0> ........................................ 0 0 DIS_BUFF<3>/DIS_BUFF<3>_D2 .X........X...X......................... 3 3 DIS_BUFF<2>/DIS_BUFF<2>_D2 .X.......X...X.......................... 3 3 DIS_BUFF<1>/DIS_BUFF<1>_D2 .X......X...X........................... 3 3 $OpTx$FX_DC$46 .X.....X...X............................ 3 3 TIME<1> ......XXXXX............................. 5 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 28/8 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\2 3 FB2_1 (b) (b) SEG<1> 2 0 0 3 FB2_2 71 I/O O SEG<0> 2 0 0 3 FB2_3 72 I/O O (unused) 0 0 0 5 FB2_4 (b) SEC 1 0 0 4 FB2_5 74 GSR/I/O (b) CNT<7> 1 0 0 4 FB2_6 75 I/O (b) CNT<6> 1 0 0 4 FB2_7 (b) (b) CNT<22> 1 0 0 4 FB2_8 76 GTS/I/O (b) CNT<9> 2 0 0 3 FB2_9 77 GTS/I/O (b) CNT<23> 2 0 0 3 FB2_10 (b) (b) CNT<21> 2 0 0 3 FB2_11 79 I/O (b) CNT<20> 2 0 0 3 FB2_12 80 I/O (b) CNT<18> 2 0 0 3 FB2_13 (b) (b) CNT<17> 2 0 0 3 FB2_14 81 I/O (b) CNT<16> 2 0 0 3 FB2_15 82 I/O (b) CNT<12> 2 0 0 3 FB2_16 83 I/O (b) CNT<11> 2 0 \/2 1 FB2_17 84 I/O (b) CNT<8> 9 4<- 0 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: CNT<0> 11: CNT<19> 20: CNT<5> 2: CNT<10> 12: CNT<1> 21: CNT<6>.LFBK 3: CNT<11>.LFBK 13: CNT<20>.LFBK 22: CNT<7>.LFBK 4: CNT<12>.LFBK 14: CNT<21>.LFBK 23: CNT<8>.LFBK 5: CNT<13> 15: CNT<22>.LFBK 24: CNT<9>.LFBK 6: CNT<14> 16: CNT<23>.LFBK 25: SEG_0/SEG_0_RSTF 7: CNT<15> 17: CNT<2> 26: SEG_0/SEG_0_SETF 8: CNT<16>.LFBK 18: CNT<3> 27: SEG_1/SEG_1_RSTF 9: CNT<17>.LFBK 19: CNT<4> 28: SEG_1/SEG_1_SETF 10: CNT<18>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs SEG<1> ..........................XX............ 2 2 SEG<0> ........................XX.............. 2 2 SEC XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<7> X..........X....XXXXX................... 7 7 CNT<6> X..........X....XXXX.................... 6 6 CNT<22> XXXXXXXXXXXXXX..XXXXXXXX................ 22 22 CNT<9> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<23> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<21> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<20> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<18> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<17> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<16> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<12> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<11> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 CNT<8> XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 19/17 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 14 I/O TIME<0> 2 0 0 3 FB3_3 15 I/O (b) TIME<6> 3 0 0 2 FB3_4 (b) (b) STATUS<1> 3 0 0 2 FB3_5 17 I/O (b) STATUS<0> 3 0 0 2 FB3_6 18 I/O (b) TIME<5> 5 0 0 0 FB3_7 (b) (b) LED<7> 4 0 0 1 FB3_8 19 I/O O LED<6> 5 0 0 0 FB3_9 20 I/O O TIME<3> 5 0 0 0 FB3_10 (b) (b) LED<5> 4 0 0 1 FB3_11 21 I/O O LED<4> 2 0 0 3 FB3_12 23 I/O O TIME<2> 5 0 0 0 FB3_13 (b) (b) LED<3> 2 0 0 3 FB3_14 24 I/O O LED<2> 4 0 0 1 FB3_15 25 I/O O LED<1> 5 0 0 0 FB3_16 26 I/O O LED<0> 4 0 \/1 0 FB3_17 31 I/O O TIME<4> 6 1<- 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: LED_0.LFBK 8: LED_7.LFBK 14: TIME<2>.LFBK 2: LED_1.LFBK 9: SEC 15: TIME<3>.LFBK 3: LED_2.LFBK 10: STATUS<0>.LFBK 16: TIME<4>.LFBK 4: LED_3.LFBK 11: STATUS<1>.LFBK 17: TIME<5>.LFBK 5: LED_4.LFBK 12: TIME<0>.LFBK 18: TIME<6>.LFBK 6: LED_5.LFBK 13: TIME<1> 19: TIME<7> 7: LED_6.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs TIME<0> ........XXXXXXXXXXX..................... 11 11 TIME<6> ........X..XXXXXXXX..................... 9 9 STATUS<1> ........XXXXXXXXXXX..................... 11 11 STATUS<0> ........XXXXXXXXXXX..................... 11 11 TIME<5> ........XXXXXXXXXXX..................... 11 11 LED<7> .......XXXXXXXXXXXX..................... 12 12 LED<6> ......X.XXXXXXXXXXX..................... 12 12 TIME<3> ........X..XXXXXXXX..................... 9 9 LED<5> .....X..XXXXXXXXXXX..................... 12 12 LED<4> ....X...X..XXXXXXXX..................... 10 10 TIME<2> ........XXXXXXXXXXX..................... 11 11 LED<3> ...X....X..XXXXXXXX..................... 10 10 LED<2> ..X.....XXXXXXXXXXX..................... 12 12 LED<1> .X......XXXXXXXXXXX..................... 12 12 LED<0> X.......XXXXXXXXXXX..................... 12 12 TIME<4> ........XXXXXXXXXXX..................... 11 11 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 31/5 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) SEL<3> 0 0 0 5 FB4_2 57 I/O O SEL<4> 0 0 0 5 FB4_3 58 I/O O (unused) 0 0 0 5 FB4_4 (b) SEL<5> 0 0 0 5 FB4_5 61 I/O O SEL<6> 1 0 0 4 FB4_6 62 I/O O CNT<19> 1 0 0 4 FB4_7 (b) (b) SEL<7> 1 0 0 4 FB4_8 63 I/O O SEG<7> 0 0 0 5 FB4_9 65 I/O O CNT<15> 1 0 0 4 FB4_10 (b) (b) SEG<6> 2 0 0 3 FB4_11 66 I/O O SEG<5> 2 0 0 3 FB4_12 67 I/O O CNT<14> 1 0 0 4 FB4_13 (b) (b) SEG<4> 2 0 0 3 FB4_14 68 I/O O SEG<3> 2 0 0 3 FB4_15 69 I/O O CNT<13> 1 0 0 4 FB4_16 (b) (b) SEG<2> 2 0 0 3 FB4_17 70 I/O O CNT<10> 1 0 0 4 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$46 12: CNT<18> 22: DIS_BUFF<1>/DIS_BUFF<1>_D2 2: $OpTx$FX_DC$48 13: CNT<1> 23: DIS_BUFF<2>/DIS_BUFF<2>_D2 3: CNT<0> 14: CNT<2> 24: DIS_BUFF<3>/DIS_BUFF<3>_D2 4: CNT<10>.LFBK 15: CNT<3> 25: SEG_2/SEG_2_SETF__$INT 5: CNT<11> 16: CNT<4> 26: SEG_3/SEG_3_RSTF 6: CNT<12> 17: CNT<5> 27: SEG_3/SEG_3_SETF 7: CNT<13>.LFBK 18: CNT<6> 28: SEG_4/SEG_4_SETF 8: CNT<14>.LFBK 19: CNT<7> 29: SEG_5/SEG_5_RSTF 9: CNT<15>.LFBK 20: CNT<8> 30: SEG_5/SEG_5_SETF 10: CNT<16> 21: CNT<9> 31: SEG_6/SEG_6_RSTF 11: CNT<17> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs SEL<3> ........................................ 0 0 SEL<4> ........................................ 0 0 SEL<5> ........................................ 0 0 SEL<6> .....XX................................. 2 2 CNT<19> ..XXXXXXXXXXXXXXXXXXX................... 19 19 SEL<7> .....XX................................. 2 2 SEG<7> ........................................ 0 0 CNT<15> ..XXXXXX....XXXXXXXXX................... 15 15 SEG<6> .X............................X......... 2 2 SEG<5> ............................XX.......... 2 2 CNT<14> ..XXXXX.....XXXXXXXXX................... 14 14 SEG<4> .X.........................X............ 2 2 SEG<3> .........................XX............. 2 2 CNT<13> ..XXXX......XXXXXXXXX................... 13 13 SEG<2> X....................XXXX............... 5 5 CNT<10> ..X.........XXXXXXXXX................... 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 0/36 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) (unused) 0 0 0 5 FB5_2 32 I/O (unused) 0 0 0 5 FB5_3 33 I/O (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 34 I/O (unused) 0 0 0 5 FB5_6 35 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 36 I/O (unused) 0 0 0 5 FB5_9 37 I/O (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 39 I/O (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 41 I/O (unused) 0 0 0 5 FB5_15 43 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O (unused) 0 0 0 5 FB5_18 (b) *********************************** FB6 *********************************** Number of function block inputs used/remaining: 11/25 Number of signals used by logic mapping into function block: 11 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use SEG_3/SEG_3_SETF 10 5<- 0 0 FB6_1 (b) (b) (unused) 0 0 0 5 FB6_2 45 I/O TIME<7> 2 0 0 3 FB6_3 46 I/O (b) SEG_6/SEG_6_RSTF 4 0 0 1 FB6_4 (b) (b) SEG_4/SEG_4_SETF 4 0 \/1 0 FB6_5 47 I/O (b) SEG_1/SEG_1_RSTF 4 1<- \/2 0 FB6_6 48 I/O (b) SEG_0/SEG_0_RSTF 4 2<- \/3 0 FB6_7 (b) (b) $OpTx$FX_DC$48 4 3<- \/4 0 FB6_8 50 I/O (b) SEG_5/SEG_5_RSTF 6 4<- \/3 0 FB6_9 51 I/O (b) SEG_3/SEG_3_RSTF 6 3<- \/2 0 FB6_10 (b) (b) SEG_2/SEG_2_SETF__$INT 6 2<- \/1 0 FB6_11 52 I/O (b) SEG_5/SEG_5_SETF 8 3<- 0 0 FB6_12 53 I/O (b) SEG_1/SEG_1_SETF 8 5<- /\2 0 FB6_13 (b) (b) SEL<0> 1 1<- /\5 0 FB6_14 54 I/O O SEL<1> 1 0 /\1 3 FB6_15 55 I/O O SEG_0/SEG_0_SETF 8 3<- 0 0 FB6_16 (b) (b) SEL<2> 0 0 /\3 2 FB6_17 56 I/O O (unused) 0 0 \/5 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: CNT<12> 5: TIME<1> 9: TIME<5> 2: CNT<13> 6: TIME<2> 10: TIME<6> 3: SEC 7: TIME<3> 11: TIME<7>.LFBK 4: TIME<0> 8: TIME<4> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs SEG_3/SEG_3_SETF X..XXXXXXXX............................. 9 9 TIME<7> ..XXXXXXXXX............................. 9 9 SEG_6/SEG_6_RSTF X..XXXXXXXX............................. 9 9 SEG_4/SEG_4_SETF X..XXXXXXXX............................. 9 9 SEG_1/SEG_1_RSTF X..XXXXXXXX............................. 9 9 SEG_0/SEG_0_RSTF X..XXXXXXXX............................. 9 9 $OpTx$FX_DC$48 X...XXX.XXX............................. 7 7 SEG_5/SEG_5_RSTF X..XXXXXXXX............................. 9 9 SEG_3/SEG_3_RSTF X..XXXXXXXX............................. 9 9 SEG_2/SEG_2_SETF__$INT X..XXXXXXXX............................. 9 9 SEG_5/SEG_5_SETF X..XXXXXXXX............................. 9 9 SEG_1/SEG_1_SETF X..XXXXXXXX............................. 9 9 SEL<0> XX...................................... 2 2 SEL<1> XX...................................... 2 2 SEG_0/SEG_0_SETF X..XXXXXXXX............................. 9 9 SEL<2> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$46 <= ((CNT(12) AND TIME(4)) OR (NOT CNT(12) AND TIME(0))); $OpTx$FX_DC$48 <= ((SEG_0/SEG_0_RSTF.EXP) OR (NOT CNT(12) AND NOT TIME(3))); FTCPE_CNT0: FTCPE port map (CNT(0),'1',CLK,'0','0'); FTCPE_CNT1: FTCPE port map (CNT(1),CNT(0).LFBK,CLK,'0','0'); FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),CLK,'0','0'); CNT_T(2) <= (CNT(0).LFBK AND CNT(1).LFBK); FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),CLK,'0','0'); CNT_T(3) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK); FTCPE_CNT4: FTCPE port map (CNT(4),CNT_T(4),CLK,'0','0'); CNT_T(4) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK); FTCPE_CNT5: FTCPE port map (CNT(5),CNT_T(5),CLK,'0','0'); CNT_T(5) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK AND CNT(4).LFBK); FTCPE_CNT6: FTCPE port map (CNT(6),CNT_T(6),CLK,'0','0'); CNT_T(6) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5)); FTCPE_CNT7: FTCPE port map (CNT(7),CNT_T(7),CLK,'0','0'); CNT_T(7) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6).LFBK); FTCPE_CNT8: FTCPE port map (CNT(8),CNT_T(8),CLK,'0','0'); CNT_T(8) <= ((NOT CNT(0)) OR (NOT CNT(1)) OR (NOT CNT(2)) OR (NOT CNT(3)) OR (NOT CNT(4)) OR (EXP0_.EXP) OR (CNT(11).EXP)); FTCPE_CNT9: FTCPE port map (CNT(9),CNT_T(9),CLK,'0','0'); CNT_T(9) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT10: FTCPE port map (CNT(10),CNT_T(10),CLK,'0','0'); CNT_T(10) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9)); FTCPE_CNT11: FTCPE port map (CNT(11),CNT_T(11),CLK,'0','0'); CNT_T(11) <= ((CNT(0) AND CNT(10) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT12: FTCPE port map (CNT(12),CNT_T(12),CLK,'0','0'); CNT_T(12) <= ((CNT(0) AND CNT(10) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(11).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT13: FTCPE port map (CNT(13),CNT_T(13),CLK,'0','0'); CNT_T(13) <= (CNT(12) AND CNT(0) AND CNT(11) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND CNT(10).LFBK); FTCPE_CNT14: FTCPE port map (CNT(14),CNT_T(14),CLK,'0','0'); CNT_T(14) <= (CNT(12) AND CNT(0) AND CNT(11) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND CNT(10).LFBK AND CNT(13).LFBK); FTCPE_CNT15: FTCPE port map (CNT(15),CNT_T(15),CLK,'0','0'); CNT_T(15) <= (CNT(12) AND CNT(0) AND CNT(11) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND CNT(10).LFBK AND CNT(13).LFBK AND CNT(14).LFBK); FTCPE_CNT16: FTCPE port map (CNT(16),CNT_T(16),CLK,'0','0'); CNT_T(16) <= ((CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT17: FTCPE port map (CNT(17),CNT_T(17),CLK,'0','0'); CNT_T(17) <= ((CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT18: FTCPE port map (CNT(18),CNT_T(18),CLK,'0','0'); CNT_T(18) <= ((CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT19: FTCPE port map (CNT(19),CNT_T(19),CLK,'0','0'); CNT_T(19) <= (CNT(12) AND CNT(0) AND CNT(11) AND CNT(16) AND CNT(17) AND CNT(18) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(6) AND CNT(7) AND CNT(8) AND CNT(9) AND CNT(10).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK); FTCPE_CNT20: FTCPE port map (CNT(20),CNT_T(20),CLK,'0','0'); CNT_T(20) <= ((CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT21: FTCPE port map (CNT(21),CNT_T(21),CLK,'0','0'); CNT_T(21) <= ((CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); FTCPE_CNT22: FTCPE port map (CNT(22),CNT_T(22),CLK,'0','0'); CNT_T(22) <= (CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK); FTCPE_CNT23: FTCPE port map (CNT(23),CNT_T(23),CLK,'0','0'); CNT_T(23) <= ((CNT(13) AND CNT(0) AND CNT(10) AND CNT(14) AND CNT(15) AND CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK)); DIS_BUFF(1)/DIS_BUFF(1)_D2 <= ((CNT(12) AND TIME(5)) OR (NOT CNT(12) AND TIME(1).LFBK)); DIS_BUFF(2)/DIS_BUFF(2)_D2 <= ((CNT(12) AND TIME(6)) OR (NOT CNT(12) AND TIME(2))); DIS_BUFF(3)/DIS_BUFF(3)_D2 <= ((CNT(12) AND TIME(7)) OR (NOT CNT(12) AND TIME(3))); FTCPE_LED0: FTCPE port map (LED(0),LED_T(0),SEC,'0','0'); LED_T(0) <= ((NOT TIME(7) AND NOT TIME(1) AND NOT LED_0.LFBK AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT LED_0.LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND LED_0.LFBK AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK)); FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),SEC,'0','0'); LED_T(1) <= ((NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND NOT LED_1.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND LED_1.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND LED_1.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND NOT LED_1.LFBK)); FTCPE_LED2: FTCPE port map (LED(2),LED_T(2),SEC,'0','0'); LED_T(2) <= ((NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT LED_2.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND NOT LED_2.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND LED_2.LFBK)); FTCPE_LED3: FTCPE port map (LED(3),LED_T(3),SEC,'0','0'); LED_T(3) <= (NOT TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT LED_3.LFBK); FTCPE_LED4: FTCPE port map (LED(4),LED_T(4),SEC,'0','0'); LED_T(4) <= (NOT TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT LED_4.LFBK); FTCPE_LED5: FTCPE port map (LED(5),LED_T(5),SEC,'0','0'); LED_T(5) <= ((NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT LED_5.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND NOT LED_5.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND LED_5.LFBK)); FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),SEC,'0','0'); LED_T(6) <= ((NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND NOT LED_6.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND LED_6.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND LED_6.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND NOT LED_6.LFBK)); FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),SEC,'0','0'); LED_T(7) <= ((NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT LED_7.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK AND NOT LED_7.LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK AND LED_7.LFBK)); FTCPE_SEC: FTCPE port map (SEC,SEC_T,CLK,'0','0'); SEC_T <= (NOT CNT(13) AND CNT(0) AND NOT CNT(10) AND NOT CNT(14) AND NOT CNT(15) AND NOT CNT(19) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND CNT(5) AND CNT(12).LFBK AND CNT(11).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(20).LFBK AND CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND NOT CNT(8).LFBK AND CNT(9).LFBK AND CNT(23).LFBK); FDCPE_SEG0: FDCPE port map (SEG(0),'0','0',SEG_0/SEG_0_RSTF,SEG_0/SEG_0_SETF); FDCPE_SEG1: FDCPE port map (SEG(1),'0','0',SEG_1/SEG_1_RSTF,SEG_1/SEG_1_SETF); FDCPE_SEG2: FDCPE port map (SEG(2),'0','0',SEG_CLR(2),NOT SEG_2/SEG_2_SETF__$INT); SEG_CLR(2) <= (DIS_BUFF(1)/DIS_BUFF(1)_D2 AND NOT DIS_BUFF(2)/DIS_BUFF(2)_D2 AND NOT DIS_BUFF(3)/DIS_BUFF(3)_D2 AND NOT $OpTx$FX_DC$46); FDCPE_SEG3: FDCPE port map (SEG(3),'0','0',SEG_3/SEG_3_RSTF,SEG_3/SEG_3_SETF); FDCPE_SEG4: FDCPE port map (SEG(4),'0','0',SEG_CLR(4),SEG_4/SEG_4_SETF); SEG_CLR(4) <= (NOT SEG_4/SEG_4_SETF AND $OpTx$FX_DC$48); FDCPE_SEG5: FDCPE port map (SEG(5),'0','0',SEG_5/SEG_5_RSTF,SEG_5/SEG_5_SETF); FDCPE_SEG6: FDCPE port map (SEG(6),'0','0',SEG_6/SEG_6_RSTF,SEG_PRE(6)); SEG_PRE(6) <= ($OpTx$FX_DC$48 AND NOT SEG_6/SEG_6_RSTF); SEG(7) <= '0'; SEG_0/SEG_0_RSTF <= ((SEG_1/SEG_1_RSTF.EXP) OR (NOT CNT(12) AND TIME(0) AND NOT TIME(1) AND NOT TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(0) AND NOT TIME(1) AND TIME(2) AND NOT TIME(3))); SEG_0/SEG_0_SETF <= ((SEG_7_OBUF$BUF2.EXP) OR (CNT(12) AND TIME(5) AND NOT TIME(7).LFBK) OR (NOT CNT(12) AND TIME(1) AND NOT TIME(3)) OR (NOT CNT(12) AND TIME(0) AND TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(0) AND NOT TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(1) AND NOT TIME(2) AND TIME(3))); SEG_1/SEG_1_RSTF <= ((SEG_4/SEG_4_SETF.EXP) OR (CNT(12) AND NOT TIME(4) AND TIME(5) AND TIME(6) AND NOT TIME(7).LFBK) OR (NOT CNT(12) AND TIME(0) AND NOT TIME(1) AND TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(0) AND TIME(1) AND TIME(2) AND NOT TIME(3))); SEG_1/SEG_1_SETF <= ((SEL_0_OBUF.EXP) OR (CNT(12) AND NOT TIME(5) AND NOT TIME(6)) OR (NOT CNT(12) AND NOT TIME(1) AND NOT TIME(2)) OR (NOT CNT(12) AND NOT TIME(2) AND NOT TIME(3))); SEG_2/SEG_2_SETF__$INT <= ((SEG_3/SEG_3_RSTF.EXP) OR (CNT(12) AND TIME(5) AND TIME(7).LFBK) OR (CNT(12) AND TIME(6) AND TIME(7).LFBK) OR (NOT CNT(12) AND TIME(1) AND TIME(3)) OR (NOT CNT(12) AND TIME(2) AND TIME(3))); SEG_3/SEG_3_RSTF <= ((SEG_5/SEG_5_RSTF.EXP) OR (NOT CNT(12) AND TIME(0) AND TIME(1) AND TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND TIME(0) AND NOT TIME(1) AND NOT TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(0) AND NOT TIME(1) AND TIME(2) AND NOT TIME(3))); SEG_3/SEG_3_SETF <= ((EXP1_.EXP) OR (CNT(12) AND NOT TIME(4) AND NOT TIME(5) AND NOT TIME(6)) OR (NOT CNT(12) AND NOT TIME(0) AND TIME(1) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(0) AND NOT TIME(1) AND NOT TIME(2)) OR (NOT CNT(12) AND TIME(1) AND NOT TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(1) AND NOT TIME(2) AND TIME(3))); SEG_4/SEG_4_SETF <= ((CNT(12) AND NOT TIME(4) AND TIME(5) AND NOT TIME(7).LFBK) OR (CNT(12) AND NOT TIME(4) AND NOT TIME(5) AND NOT TIME(6)) OR (NOT CNT(12) AND NOT TIME(0) AND TIME(1) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(0) AND NOT TIME(1) AND NOT TIME(2))); SEG_5/SEG_5_RSTF <= (($OpTx$FX_DC$48.EXP) OR (NOT CNT(12) AND TIME(0) AND TIME(1) AND NOT TIME(3)) OR (NOT CNT(12) AND TIME(0) AND NOT TIME(2) AND NOT TIME(3))); SEG_5/SEG_5_SETF <= ((SEG_2/SEG_2_SETF__$INT.EXP) OR (SEG_1/SEG_1_SETF.EXP) OR (CNT(12) AND NOT TIME(4) AND NOT TIME(5) AND NOT TIME(6)) OR (NOT CNT(12) AND NOT TIME(0) AND NOT TIME(1) AND NOT TIME(2)) OR (NOT CNT(12) AND NOT TIME(0) AND TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(1) AND TIME(2) AND NOT TIME(3)) OR (NOT CNT(12) AND NOT TIME(1) AND NOT TIME(2) AND TIME(3))); SEG_6/SEG_6_RSTF <= ((CNT(12) AND NOT TIME(5) AND NOT TIME(6) AND NOT TIME(7).LFBK) OR (NOT CNT(12) AND NOT TIME(1) AND NOT TIME(2) AND NOT TIME(3)) OR (CNT(12) AND TIME(4) AND TIME(5) AND TIME(6) AND NOT TIME(7).LFBK) OR (NOT CNT(12) AND TIME(0) AND TIME(1) AND TIME(2) AND NOT TIME(3))); SEL(0) <= SEL_1_OBUF.EXP; SEL(1) <= (CNT(12) AND NOT CNT(13)); SEL(2) <= '0'; SEL(3) <= '0'; SEL(4) <= '0'; SEL(5) <= '0'; SEL(6) <= (NOT CNT(12) AND CNT(13).LFBK); SEL(7) <= (CNT(12) AND CNT(13).LFBK); FTCPE_STATUS0: FTCPE port map (STATUS(0),STATUS_T(0),SEC,'0','0'); STATUS_T(0) <= ((NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK)); FTCPE_STATUS1: FTCPE port map (STATUS(1),STATUS_T(1),SEC,'0','0'); STATUS_T(1) <= ((NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK)); FTCPE_TIME0: FTCPE port map (TIME(0),TIME_T(0),SEC,'0','0'); TIME_T(0) <= (NOT TIME(7) AND NOT TIME(1) AND STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND STATUS(1).LFBK); FTCPE_TIME1: FTCPE port map (TIME(1),TIME_T(1),SEC,'0','0'); TIME_T(1) <= ((TIME(0)) OR (NOT TIME(2) AND NOT TIME(3) AND NOT TIME(1).LFBK)); FTCPE_TIME2: FTCPE port map (TIME(2),TIME_T(2),SEC,'0','0'); TIME_T(2) <= ((NOT TIME(1) AND NOT TIME(0).LFBK AND TIME(2).LFBK) OR (NOT TIME(1) AND NOT TIME(0).LFBK AND TIME(3).LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK) OR (NOT TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT STATUS(1).LFBK)); FTCPE_TIME3: FTCPE port map (TIME(3),TIME_T(3),SEC,'0','0'); TIME_T(3) <= ((TIME(1)) OR (TIME(0).LFBK) OR (TIME(2).LFBK) OR (NOT TIME(7) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(6).LFBK AND NOT TIME(3).LFBK)); FTCPE_TIME4: FTCPE port map (TIME(4),TIME_T(4),SEC,'0','0'); TIME_T(4) <= ((LED_0.EXP) OR (TIME(7) AND NOT TIME(1) AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND TIME(4).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND TIME(5).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK)); FTCPE_TIME5: FTCPE port map (TIME(5),TIME_T(5),SEC,'0','0'); TIME_T(5) <= ((TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND NOT TIME(4).LFBK AND TIME(5).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND NOT TIME(4).LFBK AND TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND NOT STATUS(0).LFBK AND NOT TIME(4).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK AND NOT STATUS(1).LFBK)); FTCPE_TIME6: FTCPE port map (TIME(6),TIME_T(6),SEC,'0','0'); TIME_T(6) <= ((TIME(7) AND NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK) OR (NOT TIME(1) AND NOT TIME(4).LFBK AND NOT TIME(5).LFBK AND TIME(6).LFBK AND NOT TIME(0).LFBK AND NOT TIME(2).LFBK AND NOT TIME(3).LFBK)); FTCPE_TIME7: FTCPE port map (TIME(7),TIME_T(7),SEC,'0','0'); TIME_T(7) <= (NOT TIME(4) AND NOT TIME(5) AND NOT TIME(6) AND NOT TIME(0) AND NOT TIME(1) AND NOT TIME(2) AND NOT TIME(3) AND TIME(7).LFBK); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-10-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-10-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 43 TIE 2 TIE 44 TIE 3 TIE 45 TIE 4 TIE 46 TIE 5 TIE 47 TIE 6 TIE 48 TIE 7 TIE 49 GND 8 GND 50 TIE 9 CLK 51 TIE 10 TIE 52 TIE 11 TIE 53 TIE 12 TIE 54 SEL<0> 13 TIE 55 SEL<1> 14 TIE 56 SEL<2> 15 TIE 57 SEL<3> 16 GND 58 SEL<4> 17 TIE 59 TDO 18 TIE 60 GND 19 LED<7> 61 SEL<5> 20 LED<6> 62 SEL<6> 21 LED<5> 63 SEL<7> 22 VCC 64 VCC 23 LED<4> 65 SEG<7> 24 LED<3> 66 SEG<6> 25 LED<2> 67 SEG<5> 26 LED<1> 68 SEG<4> 27 GND 69 SEG<3> 28 TDI 70 SEG<2> 29 TMS 71 SEG<1> 30 TCK 72 SEG<0> 31 LED<0> 73 VCC 32 TIE 74 TIE 33 TIE 75 TIE 34 TIE 76 TIE 35 TIE 77 TIE 36 TIE 78 VCC 37 TIE 79 TIE 38 VCC 80 TIE 39 TIE 81 TIE 40 TIE 82 TIE 41 TIE 83 TIE 42 GND 84 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-10-PC84 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25