Equations

********** Mapped Logic **********
FDCPE_Mtridata_bps_start_rx: FDCPE port map (Mtridata_bps_start_rx,Mtridata_bps_start_rx_D,CLK,'0','0');
     Mtridata_bps_start_rx_D <= ((num_rx(0).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (num_rx(1).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (NOT num_rx(2).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (NOT num_rx(3).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (NOT rs232_rx0 AND NOT rs232_rx1 AND rs232_rx2 AND rs232_rx3));
FTCPE_Mtridata_bps_start_tx: FTCPE port map (Mtridata_bps_start_tx,Mtridata_bps_start_tx_T,CLK,'0','0');
     Mtridata_bps_start_tx_T <= ((NOT rx_int1 AND rx_int2.LFBK AND
      NOT Mtridata_bps_start_tx.LFBK)
      OR (rx_int1 AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND
      num_tx(0).LFBK AND num_tx(3).LFBK AND Mtridata_bps_start_tx.LFBK)
      OR (NOT num_tx(2).LFBK AND num_tx(1).LFBK AND num_tx(0).LFBK AND
      num_tx(3).LFBK AND NOT rx_int2.LFBK AND Mtridata_bps_start_tx.LFBK));
FDCPE_RS232_TX: FDCPE port map (RS232_TX,RS232_TX_D,CLK,'0',NOT RST_B);
     RS232_TX_D <= ((num_rx(3).EXP)
      OR (num_rx(2).EXP)
      OR (NOT clk_bps_tx AND NOT rs232_tx_r.LFBK)
      OR (NOT rs232_tx_r.LFBK AND NOT tx_en.LFBK)
      OR (clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND
      NOT num_tx(1).LFBK AND NOT num_tx(0).LFBK AND NOT num_tx(3).LFBK)
      OR (clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND
      NOT num_tx(1).LFBK AND NOT num_tx(0).LFBK AND NOT RX_DATA(7).PIN)
      OR (clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND
      NOT num_tx(0).LFBK AND NOT num_tx(3).LFBK AND NOT RX_DATA(1).PIN));
FTCPE_RX_DATA0: FTCPE port map (RX_DATA(0),RX_DATA_T(0),CLK,NOT RST_B,'0');
     RX_DATA_T(0) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(0).LFBK AND
      NOT rx_temp_data(0).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(0).LFBK AND
      rx_temp_data(0).LFBK));
FTCPE_RX_DATA1: FTCPE port map (RX_DATA(1),RX_DATA_T(1),CLK,NOT RST_B,'0');
     RX_DATA_T(1) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(1).LFBK AND
      NOT rx_temp_data(1).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(1).LFBK AND
      rx_temp_data(1).LFBK));
FTCPE_RX_DATA2: FTCPE port map (RX_DATA(2),RX_DATA_T(2),CLK,NOT RST_B,'0');
     RX_DATA_T(2) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(2).LFBK AND
      NOT rx_temp_data(2).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(2).LFBK AND
      rx_temp_data(2).LFBK));
FTCPE_RX_DATA3: FTCPE port map (RX_DATA(3),RX_DATA_T(3),CLK,NOT RST_B,'0');
     RX_DATA_T(3) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(3).LFBK AND
      NOT rx_temp_data(3).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(3).LFBK AND
      rx_temp_data(3).LFBK));
FTCPE_RX_DATA4: FTCPE port map (RX_DATA(4),RX_DATA_T(4),CLK,NOT RST_B,'0');
     RX_DATA_T(4) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(4).LFBK AND
      NOT rx_temp_data(4).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(4).LFBK AND
      rx_temp_data(4).LFBK));
FTCPE_RX_DATA5: FTCPE port map (RX_DATA(5),RX_DATA_T(5),CLK,NOT RST_B,'0');
     RX_DATA_T(5) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(5).LFBK AND
      NOT rx_temp_data(5).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(5).LFBK AND
      rx_temp_data(5).LFBK));
FTCPE_RX_DATA6: FTCPE port map (RX_DATA(6),RX_DATA_T(6),CLK,NOT RST_B,'0');
     RX_DATA_T(6) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(6).LFBK AND
      NOT rx_temp_data(6).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(6).LFBK AND
      rx_temp_data(6).LFBK));
FTCPE_RX_DATA7: FTCPE port map (RX_DATA(7),RX_DATA_T(7),CLK,NOT RST_B,'0');
     RX_DATA_T(7) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND rx_data_rx(7).LFBK AND
      NOT rx_temp_data(7).LFBK)
      OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND
      num_rx(2) AND num_rx(3) AND NOT rx_data_rx(7).LFBK AND
      rx_temp_data(7).LFBK));
FDCPE_bps_start_rx: FDCPE port map (bps_start_rx,bps_start_rx_D,CLK,'0','0');
     bps_start_rx_D <= ((EXP0_.EXP)
      OR (num_rx(0).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (num_rx(1).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (NOT num_rx(2).LFBK AND Mtridata_bps_start_rx.LFBK)
      OR (NOT num_rx(3).LFBK AND Mtridata_bps_start_rx.LFBK));
FDCPE_bps_start_tx: FDCPE port map (bps_start_tx,bps_start_tx_D,CLK,'0','0');
     bps_start_tx_D <= ((rx_int1 AND NOT Mtridata_bps_start_tx.LFBK)
      OR (NOT rx_int2.LFBK AND NOT Mtridata_bps_start_tx.LFBK)
      OR (rx_int1 AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND
      num_tx(0).LFBK AND num_tx(3).LFBK)
      OR (NOT num_tx(2).LFBK AND num_tx(1).LFBK AND num_tx(0).LFBK AND
      num_tx(3).LFBK AND NOT rx_int2.LFBK));
FDCPE_clk_bps_rx: FDCPE port map (clk_bps_rx,clk_bps_rx_D,CLK,NOT RST_B,'0');
     clk_bps_rx_D <= (NOT cnt_rx(0).LFBK AND cnt_rx(10).LFBK AND
      NOT cnt_rx(11).LFBK AND cnt_rx(1).LFBK AND NOT cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      NOT cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK);
FDCPE_clk_bps_tx: FDCPE port map (clk_bps_tx,clk_bps_tx_D,CLK,NOT RST_B,'0');
     clk_bps_tx_D <= (NOT cnt_tx(11) AND NOT cnt_tx(2) AND NOT cnt_tx(0).LFBK AND
      cnt_tx(10).LFBK AND cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND
      cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND NOT cnt_tx(8).LFBK AND
      NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK);
FTCPE_cnt_rx0: FTCPE port map (cnt_rx(0),cnt_rx_T(0),CLK,NOT RST_B,'0');
     cnt_rx_T(0) <= ((NOT bps_start_rx AND NOT cnt_rx(0).LFBK)
      OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));
FDCPE_cnt_rx1: FDCPE port map (cnt_rx(1),cnt_rx_D(1),CLK,NOT RST_B,'0');
     cnt_rx_D(1) <= ((bps_start_rx AND cnt_rx(0).LFBK AND NOT cnt_rx(1).LFBK)
      OR (bps_start_rx AND NOT cnt_rx(0).LFBK AND cnt_rx(1).LFBK));
FTCPE_cnt_rx2: FTCPE port map (cnt_rx(2),cnt_rx_T(2),CLK,NOT RST_B,'0');
     cnt_rx_T(2) <= ((NOT bps_start_rx AND cnt_rx(2).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK)
      OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));
FTCPE_cnt_rx3: FTCPE port map (cnt_rx(3),cnt_rx_T(3),CLK,NOT RST_B,'0');
     cnt_rx_T(3) <= ((NOT bps_start_rx AND cnt_rx(3).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK));
FTCPE_cnt_rx4: FTCPE port map (cnt_rx(4),cnt_rx_T(4),CLK,NOT RST_B,'0');
     cnt_rx_T(4) <= ((NOT bps_start_rx AND cnt_rx(4).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK));
FTCPE_cnt_rx5: FTCPE port map (cnt_rx(5),cnt_rx_T(5),CLK,NOT RST_B,'0');
     cnt_rx_T(5) <= ((NOT bps_start_rx AND cnt_rx(5).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK));
FTCPE_cnt_rx6: FTCPE port map (cnt_rx(6),cnt_rx_T(6),CLK,NOT RST_B,'0');
     cnt_rx_T(6) <= ((NOT bps_start_rx AND cnt_rx(6).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK)
      OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));
FTCPE_cnt_rx7: FTCPE port map (cnt_rx(7),cnt_rx_T(7),CLK,NOT RST_B,'0');
     cnt_rx_T(7) <= ((NOT bps_start_rx AND cnt_rx(7).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND
      cnt_rx(6).LFBK)
      OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));
FTCPE_cnt_rx8: FTCPE port map (cnt_rx(8),cnt_rx_T(8),CLK,NOT RST_B,'0');
     cnt_rx_T(8) <= ((NOT bps_start_rx AND cnt_rx(8).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND
      cnt_rx(6).LFBK AND cnt_rx(7).LFBK)
      OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));
FTCPE_cnt_rx9: FTCPE port map (cnt_rx(9),cnt_rx_T(9),CLK,NOT RST_B,'0');
     cnt_rx_T(9) <= ((NOT bps_start_rx AND cnt_rx(9).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND
      cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND cnt_rx(8).LFBK));
FTCPE_cnt_rx10: FTCPE port map (cnt_rx(10),cnt_rx_T(10),CLK,NOT RST_B,'0');
     cnt_rx_T(10) <= ((NOT bps_start_rx AND cnt_rx(10).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND
      cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND
      cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND cnt_rx(8).LFBK AND cnt_rx(9).LFBK));
FTCPE_cnt_rx11: FTCPE port map (cnt_rx(11),cnt_rx_T(11),CLK,NOT RST_B,'0');
     cnt_rx_T(11) <= ((NOT bps_start_rx AND cnt_rx(11).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(10).LFBK AND
      cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND
      cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND cnt_rx(8).LFBK AND
      cnt_rx(9).LFBK)
      OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND
      NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));
FTCPE_cnt_rx12: FTCPE port map (cnt_rx(12),cnt_rx_T(12),CLK,NOT RST_B,'0');
     cnt_rx_T(12) <= ((NOT bps_start_rx AND cnt_rx(12).LFBK)
      OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(10).LFBK AND
      cnt_rx(11).LFBK AND cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND
      cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND
      cnt_rx(8).LFBK AND cnt_rx(9).LFBK));
FTCPE_cnt_tx0: FTCPE port map (cnt_tx(0),cnt_tx_T(0),CLK,NOT RST_B,'0');
     cnt_tx_T(0) <= ((NOT bps_start_tx AND NOT cnt_tx(0).LFBK)
      OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND
      NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND
      NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND
      NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));
FDCPE_cnt_tx1: FDCPE port map (cnt_tx(1),cnt_tx_D(1),CLK,NOT RST_B,'0');
     cnt_tx_D(1) <= ((bps_start_tx AND cnt_tx(0).LFBK AND NOT cnt_tx(1).LFBK)
      OR (bps_start_tx AND NOT cnt_tx(0).LFBK AND cnt_tx(1).LFBK));
FTCPE_cnt_tx2: FTCPE port map (cnt_tx(2),cnt_tx_T(2),CLK,NOT RST_B,'0');
     cnt_tx_T(2) <= ((NOT bps_start_tx AND cnt_tx(2).LFBK)
      OR (cnt_tx(0) AND cnt_tx(1) AND bps_start_tx)
      OR (NOT cnt_tx(0) AND NOT cnt_tx(10) AND NOT cnt_tx(1) AND NOT cnt_tx(3) AND
      NOT cnt_tx(4) AND NOT cnt_tx(5) AND cnt_tx(6) AND cnt_tx(7) AND cnt_tx(8) AND
      NOT cnt_tx(9) AND NOT cnt_tx(12) AND cnt_tx(11).LFBK AND cnt_tx(2).LFBK));
FTCPE_cnt_tx3: FTCPE port map (cnt_tx(3),cnt_tx_T(3),CLK,NOT RST_B,'0');
     cnt_tx_T(3) <= ((NOT bps_start_tx AND cnt_tx(3).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK));
FTCPE_cnt_tx4: FTCPE port map (cnt_tx(4),cnt_tx_T(4),CLK,NOT RST_B,'0');
     cnt_tx_T(4) <= ((NOT bps_start_tx AND cnt_tx(4).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK));
FTCPE_cnt_tx5: FTCPE port map (cnt_tx(5),cnt_tx_T(5),CLK,NOT RST_B,'0');
     cnt_tx_T(5) <= ((NOT bps_start_tx AND cnt_tx(5).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK));
FTCPE_cnt_tx6: FTCPE port map (cnt_tx(6),cnt_tx_T(6),CLK,NOT RST_B,'0');
     cnt_tx_T(6) <= ((NOT bps_start_tx AND cnt_tx(6).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK)
      OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND
      NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND
      NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND
      NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));
FTCPE_cnt_tx7: FTCPE port map (cnt_tx(7),cnt_tx_T(7),CLK,NOT RST_B,'0');
     cnt_tx_T(7) <= ((NOT bps_start_tx AND cnt_tx(7).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND
      cnt_tx(6).LFBK)
      OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND
      NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND
      NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND
      NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));
FTCPE_cnt_tx8: FTCPE port map (cnt_tx(8),cnt_tx_T(8),CLK,NOT RST_B,'0');
     cnt_tx_T(8) <= ((NOT bps_start_tx AND cnt_tx(8).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND
      cnt_tx(6).LFBK AND cnt_tx(7).LFBK)
      OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND
      NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND
      NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND
      NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));
FTCPE_cnt_tx9: FTCPE port map (cnt_tx(9),cnt_tx_T(9),CLK,NOT RST_B,'0');
     cnt_tx_T(9) <= ((NOT bps_start_tx AND cnt_tx(9).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND
      cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK));
FTCPE_cnt_tx10: FTCPE port map (cnt_tx(10),cnt_tx_T(10),CLK,NOT RST_B,'0');
     cnt_tx_T(10) <= ((NOT bps_start_tx AND cnt_tx(10).LFBK)
      OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND
      cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND
      cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND cnt_tx(9).LFBK));
FTCPE_cnt_tx11: FTCPE port map (cnt_tx(11),cnt_tx_T(11),CLK,NOT RST_B,'0');
     cnt_tx_T(11) <= ((NOT bps_start_tx AND cnt_tx(11).LFBK)
      OR (cnt_tx(0) AND cnt_tx(10) AND cnt_tx(1) AND cnt_tx(3) AND
      cnt_tx(4) AND cnt_tx(5) AND cnt_tx(6) AND cnt_tx(7) AND cnt_tx(8) AND
      cnt_tx(9) AND bps_start_tx AND cnt_tx(2).LFBK)
      OR (NOT cnt_tx(0) AND NOT cnt_tx(10) AND NOT cnt_tx(1) AND NOT cnt_tx(3) AND
      NOT cnt_tx(4) AND NOT cnt_tx(5) AND cnt_tx(6) AND cnt_tx(7) AND cnt_tx(8) AND
      NOT cnt_tx(9) AND NOT cnt_tx(12) AND cnt_tx(11).LFBK AND cnt_tx(2).LFBK));
FTCPE_cnt_tx12: FTCPE port map (cnt_tx(12),cnt_tx_T(12),CLK,NOT RST_B,'0');
     cnt_tx_T(12) <= ((NOT bps_start_tx AND cnt_tx(12).LFBK)
      OR (cnt_tx(11) AND cnt_tx(2) AND bps_start_tx AND
      cnt_tx(0).LFBK AND cnt_tx(10).LFBK AND cnt_tx(1).LFBK AND
      cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND
      cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND cnt_tx(9).LFBK));
FTCPE_num_rx0: FTCPE port map (num_rx(0),num_rx_T(0),CLK,NOT RST_B,'0');
     num_rx_T(0) <= (clk_bps_rx AND rx_int.LFBK);
FTCPE_num_rx1: FTCPE port map (num_rx(1),num_rx_T(1),CLK,NOT RST_B,'0');
     num_rx_T(1) <= (clk_bps_rx AND rx_int.LFBK AND num_rx(0).LFBK);
FTCPE_num_rx2: FTCPE port map (num_rx(2),num_rx_T(2),CLK,NOT RST_B,'0');
     num_rx_T(2) <= ((clk_bps_rx AND rx_int.LFBK AND num_rx(0).LFBK AND
      num_rx(1).LFBK)
      OR (NOT clk_bps_rx AND rx_int.LFBK AND NOT num_rx(0).LFBK AND
      NOT num_rx(1).LFBK AND num_rx(2).LFBK AND num_rx(3).LFBK));
FTCPE_num_rx3: FTCPE port map (num_rx(3),num_rx_T(3),CLK,NOT RST_B,'0');
     num_rx_T(3) <= ((clk_bps_rx AND rx_int.LFBK AND num_rx(0).LFBK AND
      num_rx(1).LFBK AND num_rx(2).LFBK)
      OR (NOT clk_bps_rx AND rx_int.LFBK AND NOT num_rx(0).LFBK AND
      NOT num_rx(1).LFBK AND num_rx(2).LFBK AND num_rx(3).LFBK));
FTCPE_num_tx0: FTCPE port map (num_tx(0),num_tx_T(0),CLK,NOT RST_B,'0');
     num_tx_T(0) <= ((clk_bps_tx AND tx_en.LFBK)
      OR (tx_en.LFBK AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND
      num_tx(0).LFBK AND num_tx(3).LFBK));
FTCPE_num_tx1: FTCPE port map (num_tx(1),num_tx_T(1),CLK,NOT RST_B,'0');
     num_tx_T(1) <= ((clk_bps_tx AND tx_en.LFBK AND num_tx(0).LFBK)
      OR (tx_en.LFBK AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND
      num_tx(0).LFBK AND num_tx(3).LFBK));
FTCPE_num_tx2: FTCPE port map (num_tx(2),num_tx_T(2),CLK,NOT RST_B,'0');
     num_tx_T(2) <= (clk_bps_tx AND tx_en.LFBK AND num_tx(1).LFBK AND
      num_tx(0).LFBK);
FTCPE_num_tx3: FTCPE port map (num_tx(3),num_tx_T(3),CLK,NOT RST_B,'0');
     num_tx_T(3) <= ((clk_bps_tx AND tx_en.LFBK AND num_tx(2).LFBK AND
      num_tx(1).LFBK AND num_tx(0).LFBK)
      OR (NOT clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND
      num_tx(1).LFBK AND num_tx(0).LFBK AND num_tx(3).LFBK));
FDCPE_rs232_rx0: FDCPE port map (rs232_rx0,RS232_RX,CLK,NOT RST_B,'0');
FDCPE_rs232_rx1: FDCPE port map (rs232_rx1,rs232_rx0.LFBK,CLK,NOT RST_B,'0');
FDCPE_rs232_rx2: FDCPE port map (rs232_rx2,rs232_rx1.LFBK,CLK,NOT RST_B,'0');
FDCPE_rs232_rx3: FDCPE port map (rs232_rx3,rs232_rx2.LFBK,CLK,NOT RST_B,'0');
FDCPE_rx_int: FDCPE port map (rx_int,rx_int_D,CLK,NOT RST_B,'0');
     rx_int_D <= ((rx_int.LFBK AND num_rx(0).LFBK)
      OR (rx_int.LFBK AND num_rx(1).LFBK)
      OR (rx_int.LFBK AND NOT num_rx(2).LFBK)
      OR (rx_int.LFBK AND NOT num_rx(3).LFBK)
      OR (NOT rs232_rx0 AND NOT rs232_rx1 AND rs232_rx2 AND rs232_rx3));
FDCPE_rx_int0: FDCPE port map (rx_int0,rx_int,CLK,NOT RST_B,'0');
FDCPE_rx_int1: FDCPE port map (rx_int1,rx_int0.LFBK,CLK,NOT RST_B,'0');
FDCPE_rx_int2: FDCPE port map (rx_int2,rx_int1,CLK,NOT RST_B,'0');
FTCPE_rx_temp_data0: FTCPE port map (rx_temp_data(0),rx_temp_data_T(0),CLK,NOT RST_B,'0');
     rx_temp_data_T(0) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      NOT num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(0).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      NOT num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND rx_temp_data(0).LFBK));
FTCPE_rx_temp_data1: FTCPE port map (rx_temp_data(1),rx_temp_data_T(1),CLK,NOT RST_B,'0');
     rx_temp_data_T(1) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(1).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND rx_temp_data(1).LFBK));
FTCPE_rx_temp_data2: FTCPE port map (rx_temp_data(2),rx_temp_data_T(2),CLK,NOT RST_B,'0');
     rx_temp_data_T(2) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(2).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND rx_temp_data(2).LFBK));
FTCPE_rx_temp_data3: FTCPE port map (rx_temp_data(3),rx_temp_data_T(3),CLK,NOT RST_B,'0');
     rx_temp_data_T(3) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(3).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(3).LFBK));
FTCPE_rx_temp_data4: FTCPE port map (rx_temp_data(4),rx_temp_data_T(4),CLK,NOT RST_B,'0');
     rx_temp_data_T(4) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(4).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(4).LFBK));
FTCPE_rx_temp_data5: FTCPE port map (rx_temp_data(5),rx_temp_data_T(5),CLK,NOT RST_B,'0');
     rx_temp_data_T(5) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(5).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(5).LFBK));
FTCPE_rx_temp_data6: FTCPE port map (rx_temp_data(6),rx_temp_data_T(6),CLK,NOT RST_B,'0');
     rx_temp_data_T(6) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(6).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND
      num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(6).LFBK));
FTCPE_rx_temp_data7: FTCPE port map (rx_temp_data(7),rx_temp_data_T(7),CLK,NOT RST_B,'0');
     rx_temp_data_T(7) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      NOT num_rx(1) AND NOT num_rx(2) AND num_rx(3) AND NOT rx_temp_data(7).LFBK)
      OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND
      NOT num_rx(1) AND NOT num_rx(2) AND num_rx(3) AND rx_temp_data(7).LFBK));
FTCPE_tx_en: FTCPE port map (tx_en,tx_en_T,CLK,NOT RST_B,'0');
     tx_en_T <= ((NOT rx_int1 AND NOT tx_en.LFBK AND rx_int2.LFBK)
      OR (rx_int1 AND tx_en.LFBK AND NOT num_tx(2).LFBK AND
      num_tx(1).LFBK AND num_tx(0).LFBK AND num_tx(3).LFBK)
      OR (tx_en.LFBK AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND
      num_tx(0).LFBK AND num_tx(3).LFBK AND NOT rx_int2.LFBK));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);