********** Mapped Logic ********** |
FDCPE_CONTROL_REG0: FDCPE port map (CONTROL_REG(0),DATA_PORT(0).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG1: FDCPE port map (CONTROL_REG(1),DATA_PORT(1).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG2: FDCPE port map (CONTROL_REG(2),DATA_PORT(2).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG3: FDCPE port map (CONTROL_REG(3),DATA_PORT(3).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG4: FDCPE port map (CONTROL_REG(4),DATA_PORT(4).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG5: FDCPE port map (CONTROL_REG(5),DATA_PORT(5).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG6: FDCPE port map (CONTROL_REG(6),DATA_PORT(6).PIN,NOT ALE,'0','0'); |
FDCPE_CONTROL_REG7: FDCPE port map (CONTROL_REG(7),DATA_PORT(7).PIN,NOT ALE,'0','0'); |
DATA_PORT_I(0) <= KEY_REG(0);
DATA_PORT(0) <= DATA_PORT_I(0) when DATA_PORT_OE(0) = '1' else 'Z'; DATA_PORT_OE(0) <= NOT RD; |
DATA_PORT_I(1) <= KEY_REG(1);
DATA_PORT(1) <= DATA_PORT_I(1) when DATA_PORT_OE(1) = '1' else 'Z'; DATA_PORT_OE(1) <= NOT RD; |
DATA_PORT_I(2) <= KEY_REG(2);
DATA_PORT(2) <= DATA_PORT_I(2) when DATA_PORT_OE(2) = '1' else 'Z'; DATA_PORT_OE(2) <= NOT RD; |
DATA_PORT_I(3) <= KEY_REG(3);
DATA_PORT(3) <= DATA_PORT_I(3) when DATA_PORT_OE(3) = '1' else 'Z'; DATA_PORT_OE(3) <= NOT RD; |
DATA_PORT_I(4) <= KEY_REG(4);
DATA_PORT(4) <= DATA_PORT_I(4) when DATA_PORT_OE(4) = '1' else 'Z'; DATA_PORT_OE(4) <= NOT RD; |
DATA_PORT_I(5) <= KEY_REG(5);
DATA_PORT(5) <= DATA_PORT_I(5) when DATA_PORT_OE(5) = '1' else 'Z'; DATA_PORT_OE(5) <= NOT RD; |
DATA_PORT_I(6) <= KEY_REG(6);
DATA_PORT(6) <= DATA_PORT_I(6) when DATA_PORT_OE(6) = '1' else 'Z'; DATA_PORT_OE(6) <= NOT RD; |
DATA_PORT_I(7) <= KEY_REG(7);
DATA_PORT(7) <= DATA_PORT_I(7) when DATA_PORT_OE(7) = '1' else 'Z'; DATA_PORT_OE(7) <= NOT RD; |
FDCPE_KEY_REG0: FDCPE port map (KEY_REG(0),KEY(0),NOT RD,'0','0'); |
FDCPE_KEY_REG1: FDCPE port map (KEY_REG(1),KEY(1),NOT RD,'0','0'); |
FDCPE_KEY_REG2: FDCPE port map (KEY_REG(2),KEY(2),NOT RD,'0','0'); |
FDCPE_KEY_REG3: FDCPE port map (KEY_REG(3),KEY(3),NOT RD,'0','0'); |
FDCPE_KEY_REG4: FDCPE port map (KEY_REG(4),KEY(4),NOT RD,'0','0'); |
FDCPE_KEY_REG5: FDCPE port map (KEY_REG(5),KEY(5),NOT RD,'0','0'); |
FDCPE_KEY_REG6: FDCPE port map (KEY_REG(6),KEY(6),NOT RD,'0','0'); |
FDCPE_KEY_REG7: FDCPE port map (KEY_REG(7),KEY(7),NOT RD,'0','0'); |
FTCPE_LED0: FTCPE port map (LED(0),LED_T(0),NOT WR,'0','0');
LED_T(0) <= ((DATA_PORT(0).PIN AND CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(0).LFBK) OR (NOT DATA_PORT(0).PIN AND CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(0).LFBK)); |
FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),NOT WR,'0','0');
LED_T(1) <= ((CONTROL_REG(0) AND DATA_PORT(1).PIN AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(1).LFBK) OR (CONTROL_REG(0) AND NOT DATA_PORT(1).PIN AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(1).LFBK)); |
FTCPE_LED2: FTCPE port map (LED(2),LED_T(2),NOT WR,'0','0');
LED_T(2) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND DATA_PORT(2).PIN AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(2).LFBK) OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT DATA_PORT(2).PIN AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(2).LFBK)); |
FTCPE_LED3: FTCPE port map (LED(3),LED_T(3),NOT WR,'0','0');
LED_T(3) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND DATA_PORT(3).PIN AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(3).LFBK) OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT DATA_PORT(3).PIN AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(3).LFBK)); |
FTCPE_LED4: FTCPE port map (LED(4),LED_T(4),NOT WR,'0','0');
LED_T(4) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND DATA_PORT(4).PIN AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(4).LFBK) OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT DATA_PORT(4).PIN AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(4).LFBK)); |
FTCPE_LED5: FTCPE port map (LED(5),LED_T(5),NOT WR,'0','0');
LED_T(5) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND DATA_PORT(5).PIN AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(5).LFBK) OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT DATA_PORT(5).PIN AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(5).LFBK)); |
FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),NOT WR,'0','0');
LED_T(6) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND DATA_PORT(6).PIN AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(6).LFBK) OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT DATA_PORT(6).PIN AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(6).LFBK)); |
FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),NOT WR,'0','0');
LED_T(7) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND DATA_PORT(7).PIN AND NOT CONTROL_REG(7) AND NOT LED_REG(7).LFBK) OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT DATA_PORT(7).PIN AND NOT CONTROL_REG(7) AND LED_REG(7).LFBK)); |
FDCPE_Mtrien_KEY_REG: FDCPE port map (Mtrien_KEY_REG,Mtrien_KEY_REG_D,NOT RD,'0','0');
Mtrien_KEY_REG_D <= (NOT CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |