Equations

********** Mapped Logic **********
FTCPE_BZ_OUT: FTCPE port map (BZ_OUT,'1',BZ_OUT_C,'0','0');
     BZ_OUT_C <= (COUNTER(0).LFBK AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND
      COUNTER(14).LFBK);
FTCPE_CLK_4: FTCPE port map (CLK_4,CLK_4_T,CLK,'0','0');
     CLK_4_T <= (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK);
FTCPE_CNT0: FTCPE port map (CNT(0),'1',CLK,'0','0');
FTCPE_CNT1: FTCPE port map (CNT(1),CNT(0).LFBK,CLK,'0','0');
FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),CLK,'0','0');
     CNT_T(2) <= (CNT(0).LFBK AND CNT(1).LFBK);
FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),CLK,'0','0');
     CNT_T(3) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK);
FTCPE_CNT4: FTCPE port map (CNT(4),CNT_T(4),CLK,'0','0');
     CNT_T(4) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND
      CNT(3).LFBK);
FTCPE_CNT5: FTCPE port map (CNT(5),CNT_T(5),CLK,'0','0');
     CNT_T(5) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND
      CNT(3).LFBK AND CNT(4).LFBK);
FTCPE_CNT6: FTCPE port map (CNT(6),CNT_T(6),CLK,'0','0');
     CNT_T(6) <= ((NOT CNT(0))
      OR (NOT CNT(1))
      OR (NOT CNT(2))
      OR (NOT CNT(3))
      OR (NOT CNT(4))
      OR (CNT(10).EXP));
FTCPE_CNT7: FTCPE port map (CNT(7),CNT_T(7),CLK,'0','0');
     CNT_T(7) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
      CNT(5) AND CNT(6).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(7).LFBK AND CNT(9).LFBK AND
      NOT CNT(23).LFBK));
FTCPE_CNT8: FTCPE port map (CNT(8),CNT_T(8),CLK,'0','0');
     CNT_T(8) <= (CNT(6) AND CNT(7) AND CNT(0).LFBK AND CNT(1).LFBK AND
      CNT(2).LFBK AND CNT(3).LFBK AND CNT(4).LFBK AND CNT(5).LFBK);
FTCPE_CNT9: FTCPE port map (CNT(9),CNT_T(9),CLK,'0','0');
     CNT_T(9) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
      CNT(5) AND CNT(8) AND CNT(6).LFBK AND CNT(7).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT10: FTCPE port map (CNT(10),CNT_T(10),CLK,'0','0');
     CNT_T(10) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND
      CNT(5) AND CNT(8) AND CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT11: FTCPE port map (CNT(11),CNT_T(11),CLK,'0','0');
     CNT_T(11) <= (CNT(10) AND CNT(6) AND CNT(7) AND CNT(9) AND
      CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(8).LFBK);
FTCPE_CNT12: FTCPE port map (CNT(12),CNT_T(12),CLK,'0','0');
     CNT_T(12) <= (CNT(10) AND CNT(6) AND CNT(7) AND CNT(9) AND
      CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(8).LFBK AND CNT(11).LFBK);
FTCPE_CNT13: FTCPE port map (CNT(13),CNT_T(13),CLK,'0','0');
     CNT_T(13) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK);
FTCPE_CNT14: FTCPE port map (CNT(14),CNT_T(14),CLK,'0','0');
     CNT_T(14) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT15: FTCPE port map (CNT(15),CNT_T(15),CLK,'0','0');
     CNT_T(15) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT16: FTCPE port map (CNT(16),CNT_T(16),CLK,'0','0');
     CNT_T(16) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(6).LFBK AND
      CNT(7).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT17: FTCPE port map (CNT(17),CNT_T(17),CLK,'0','0');
     CNT_T(17) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK);
FTCPE_CNT18: FTCPE port map (CNT(18),CNT_T(18),CLK,'0','0');
     CNT_T(18) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(17).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT19: FTCPE port map (CNT(19),CNT_T(19),CLK,'0','0');
     CNT_T(19) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(17).LFBK AND CNT(18).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT20: FTCPE port map (CNT(20),CNT_T(20),CLK,'0','0');
     CNT_T(20) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(6).LFBK AND
      CNT(7).LFBK AND CNT(9).LFBK);
FTCPE_CNT21: FTCPE port map (CNT(21),CNT_T(21),CLK,'0','0');
     CNT_T(21) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(20).LFBK AND
      CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND
      NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND
      CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK AND NOT CNT(23).LFBK));
FTCPE_CNT22: FTCPE port map (CNT(22),CNT_T(22),CLK,'0','0');
     CNT_T(22) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(20).LFBK AND
      CNT(21).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK);
FTCPE_CNT23: FTCPE port map (CNT(23),CNT_T(23),CLK,'0','0');
     CNT_T(23) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND
      CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND
      CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND
      CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(20).LFBK AND
      CNT(21).LFBK AND CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND
      CNT(9).LFBK);
FTCPE_COUNTER0: FTCPE port map (COUNTER(0),COUNTER_T(0),CLK,'0','0');
     COUNTER_T(0) <= (COUNTER_BEGIN(0) AND COUNTER(0).LFBK AND
      COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND
      COUNTER(13).LFBK AND COUNTER(1).LFBK AND COUNTER(2).LFBK AND
      COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND
      COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND
      COUNTER(9).LFBK AND COUNTER(14).LFBK);
FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER_T(1),CLK,'0','0');
     COUNTER_T(1) <= ((NOT COUNTER(0).LFBK)
      OR (COUNTER_BEGIN(1) AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND
      COUNTER(14).LFBK));
FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
     COUNTER_T(2) <= ((NOT COUNTER(0).LFBK)
      OR (NOT COUNTER(1).LFBK)
      OR (COUNTER_BEGIN(2) AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND
      COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND
      COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND
      COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(14).LFBK));
FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
     COUNTER_T(3) <= ((BZ_OUT_OBUF.EXP)
      OR (NOT COUNTER(0).LFBK)
      OR (NOT COUNTER(1).LFBK));
FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
     COUNTER_T(4) <= ((COUNTER(12).EXP)
      OR (NOT COUNTER(0).LFBK));
FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
     COUNTER_T(5) <= ((COUNTER(11).EXP)
      OR (NOT COUNTER(0).LFBK)
      OR (NOT COUNTER(1).LFBK));
FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
     COUNTER_T(6) <= ((EXP3_.EXP)
      OR (NOT COUNTER(0).LFBK)
      OR (NOT COUNTER(1).LFBK));
FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
     COUNTER_T(7) <= ((EXP2_.EXP)
      OR (NOT COUNTER(0).LFBK)
      OR (NOT COUNTER(1).LFBK)
      OR (NOT COUNTER(2).LFBK)
      OR (NOT COUNTER(3).LFBK)
      OR (NOT COUNTER(4).LFBK));
FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
     COUNTER_T(8) <= ((COUNTER(6).EXP)
      OR (COUNTER(0).LFBK AND NOT COUNTER(10).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(11).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(12).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(13).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK)
      OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND
      COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND
      COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND
      NOT COUNTER(8).LFBK));
FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
     COUNTER_T(9) <= ((COUNTER(10).EXP)
      OR (COUNTER(0).LFBK AND NOT COUNTER(10).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(11).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(12).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(13).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK)
      OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND
      COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND
      COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND
      COUNTER(8).LFBK AND NOT COUNTER(9).LFBK));
FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
     COUNTER_T(10) <= ((COUNTER(5).EXP)
      OR (COUNTER(0).LFBK AND NOT COUNTER(10).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(11).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
      OR (COUNTER(0).LFBK AND NOT COUNTER(12).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK));
FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
     COUNTER_T(11) <= ((COUNTER(4).EXP)
      OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND
      NOT COUNTER(11).LFBK AND COUNTER(1).LFBK AND COUNTER(2).LFBK AND
      COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND
      COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND
      COUNTER(9).LFBK));
FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
     COUNTER_T(12) <= ((COUNTER(3).EXP)
      OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND NOT COUNTER(12).LFBK AND COUNTER(1).LFBK AND
      COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND
      COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND
      COUNTER(8).LFBK AND COUNTER(9).LFBK));
FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
     COUNTER_T(13) <= ((NOT COUNTER_BEGIN(13) AND COUNTER(0).LFBK AND
      COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
      OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND COUNTER(12).LFBK AND NOT COUNTER(13).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
      OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(1).LFBK AND
      COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND
      COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND
      COUNTER(8).LFBK AND COUNTER(9).LFBK AND NOT COUNTER(14).LFBK));
FTCPE_COUNTER14: FTCPE port map (COUNTER(14),COUNTER_T(14),CLK,'0','0');
     COUNTER_T(14) <= ((NOT COUNTER_BEGIN(14) AND COUNTER(0).LFBK AND
      COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND
      COUNTER(13).LFBK AND COUNTER(1).LFBK AND COUNTER(2).LFBK AND
      COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND
      COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND
      COUNTER(9).LFBK)
      OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND
      COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND
      COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND
      COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND
      COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND
      NOT COUNTER(14).LFBK));
FTCPE_COUNTER_BEGIN0: FTCPE port map (COUNTER_BEGIN(0),COUNTER_BEGIN_T(0),CLK_4,'0','0');
     COUNTER_BEGIN_T(0) <= ((M(2).LFBK AND NOT L(0).LFBK AND NOT COUNTER_BEGIN(0).LFBK AND
      NOT M(1).LFBK)
      OR (NOT M(2).LFBK AND NOT L(0).LFBK AND M(0).LFBK AND
      COUNTER_BEGIN(0).LFBK)
      OR (NOT M(2).LFBK AND NOT L(0).LFBK AND NOT M(0).LFBK AND
      NOT COUNTER_BEGIN(0).LFBK)
      OR (NOT M(2).LFBK AND NOT M(0).LFBK AND NOT COUNTER_BEGIN(0).LFBK AND
      NOT M(1).LFBK));
FTCPE_COUNTER_BEGIN1: FTCPE port map (COUNTER_BEGIN(1),COUNTER_BEGIN_T(1),CLK_4,'0','0');
     COUNTER_BEGIN_T(1) <= ((NOT M(2).LFBK AND NOT L(0).LFBK AND M(1).LFBK AND
      NOT COUNTER_BEGIN(1).LFBK)
      OR (NOT M(2).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND
      NOT COUNTER_BEGIN(1).LFBK)
      OR (NOT L(0).LFBK AND M(0).LFBK AND NOT M(1).LFBK AND
      COUNTER_BEGIN(1).LFBK)
      OR (NOT L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND
      NOT COUNTER_BEGIN(1).LFBK));
FDCPE_COUNTER_BEGIN2: FDCPE port map (COUNTER_BEGIN(2),COUNTER_BEGIN_D(2),CLK_4,'0','0');
     COUNTER_BEGIN_D(2) <= ((L(0).LFBK AND NOT COUNTER_BEGIN(2).LFBK)
      OR (M(2).LFBK AND M(1).LFBK AND NOT COUNTER_BEGIN(2).LFBK)
      OR (M(2).LFBK AND NOT L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK)
      OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK));
FDCPE_COUNTER_BEGIN3: FDCPE port map (COUNTER_BEGIN(3),COUNTER_BEGIN_D(3),CLK_4,'0','0');
     COUNTER_BEGIN_D(3) <= ((EXP1_.EXP)
      OR (M(2) AND NOT COUNTER_BEGIN(3).LFBK)
      OR (M(1) AND L(0) AND NOT COUNTER_BEGIN(3).LFBK)
      OR (NOT M(1) AND M(2) AND NOT L(0)));
FDCPE_COUNTER_BEGIN4: FDCPE port map (COUNTER_BEGIN(4),COUNTER_BEGIN_D(4),CLK_4,'0','0');
     COUNTER_BEGIN_D(4) <= ((COUNTER_BEGIN(14).EXP)
      OR (M(1) AND M(2) AND COUNTER_BEGIN(4).LFBK)
      OR (M(1) AND L(0) AND COUNTER_BEGIN(4).LFBK)
      OR (M(2) AND L(0) AND COUNTER_BEGIN(4).LFBK)
      OR (L(0) AND M(0) AND COUNTER_BEGIN(4).LFBK));
FTCPE_COUNTER_BEGIN5: FTCPE port map (COUNTER_BEGIN(5),COUNTER_BEGIN_T(5),CLK_4,'0','0');
     COUNTER_BEGIN_T(5) <= ((NOT M(2).LFBK AND NOT L(0).LFBK AND NOT COUNTER_BEGIN(5).LFBK)
      OR (NOT L(0).LFBK AND NOT M(1).LFBK AND NOT COUNTER_BEGIN(5).LFBK)
      OR (NOT M(2).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND
      NOT COUNTER_BEGIN(5).LFBK));
FTCPE_COUNTER_BEGIN6: FTCPE port map (COUNTER_BEGIN(6),COUNTER_BEGIN_T(6),CLK_4,'0','0');
     COUNTER_BEGIN_T(6) <= ((COUNTER_BEGIN(7).EXP)
      OR (NOT M(1) AND NOT M(2) AND NOT M(0) AND NOT COUNTER_BEGIN(6).LFBK)
      OR (NOT M(1) AND NOT L(0) AND NOT M(0) AND NOT COUNTER_BEGIN(6).LFBK)
      OR (NOT M(2) AND NOT L(0) AND M(0) AND NOT COUNTER_BEGIN(6).LFBK)
      OR (NOT M(1) AND M(2) AND NOT L(0) AND M(0) AND
      COUNTER_BEGIN(6).LFBK));
FDCPE_COUNTER_BEGIN7: FDCPE port map (COUNTER_BEGIN(7),COUNTER_BEGIN_D(7),CLK_4,'0','0');
     COUNTER_BEGIN_D(7) <= ((COUNTER_BEGIN(8).EXP)
      OR (L(0) AND NOT COUNTER_BEGIN(7).LFBK)
      OR (M(1) AND M(2) AND NOT COUNTER_BEGIN(7).LFBK)
      OR (NOT M(1) AND NOT L(0) AND M(0)));
FDCPE_COUNTER_BEGIN8: FDCPE port map (COUNTER_BEGIN(8),COUNTER_BEGIN_D(8),CLK_4,'0','0');
     COUNTER_BEGIN_D(8) <= ((CNT(0).EXP)
      OR (M(1) AND M(2) AND COUNTER_BEGIN(8).LFBK)
      OR (M(1) AND L(0) AND COUNTER_BEGIN(8).LFBK));
FTCPE_COUNTER_BEGIN9: FTCPE port map (COUNTER_BEGIN(9),COUNTER_BEGIN_T(9),CLK_4,'0','0');
     COUNTER_BEGIN_T(9) <= ((M(2).LFBK AND NOT L(0).LFBK AND NOT M(1).LFBK AND
      COUNTER_BEGIN(9).LFBK)
      OR (NOT M(2).LFBK AND NOT L(0).LFBK AND M(1).LFBK AND
      COUNTER_BEGIN(9).LFBK)
      OR (NOT M(2).LFBK AND NOT L(0).LFBK AND NOT M(1).LFBK AND
      NOT COUNTER_BEGIN(9).LFBK)
      OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND
      COUNTER_BEGIN(9).LFBK));
FTCPE_COUNTER_BEGIN10: FTCPE port map (COUNTER_BEGIN(10),COUNTER_BEGIN_T(10),CLK_4,'0','0');
     COUNTER_BEGIN_T(10) <= ((NOT L(0).LFBK AND NOT M(1).LFBK AND NOT COUNTER_BEGIN(10).LFBK)
      OR (NOT M(2).LFBK AND NOT L(0).LFBK AND M(1).LFBK AND
      COUNTER_BEGIN(10).LFBK)
      OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND
      COUNTER_BEGIN(10).LFBK));
FDCPE_COUNTER_BEGIN11: FDCPE port map (COUNTER_BEGIN(11),COUNTER_BEGIN_D(11),CLK_4,'0','0');
     COUNTER_BEGIN_D(11) <= ((COUNTER_BEGIN(3).EXP)
      OR (L(0) AND COUNTER_BEGIN(11).LFBK)
      OR (M(1) AND M(2) AND COUNTER_BEGIN(11).LFBK)
      OR (NOT M(1) AND NOT M(2) AND NOT M(0))
      OR (NOT M(1) AND NOT L(0) AND NOT M(0)));
FDCPE_COUNTER_BEGIN12: FDCPE port map (COUNTER_BEGIN(12),COUNTER_BEGIN_D(12),CLK_4,'0','0');
     COUNTER_BEGIN_D(12) <= ((L(0).LFBK AND NOT COUNTER_BEGIN(12).LFBK)
      OR (M(2).LFBK AND M(1).LFBK AND NOT COUNTER_BEGIN(12).LFBK)
      OR (NOT L(0).LFBK AND M(0).LFBK AND NOT M(1).LFBK)
      OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK));
FDCPE_COUNTER_BEGIN13: FDCPE port map (COUNTER_BEGIN(13),COUNTER_BEGIN_D(13),CLK_4,'0','0');
     COUNTER_BEGIN_D(13) <= ((L(0).LFBK AND NOT COUNTER_BEGIN(13).LFBK)
      OR (M(2).LFBK AND M(1).LFBK AND NOT COUNTER_BEGIN(13).LFBK)
      OR (M(2).LFBK AND NOT L(0).LFBK AND M(0).LFBK AND NOT M(1).LFBK)
      OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK));
FDCPE_COUNTER_BEGIN14: FDCPE port map (COUNTER_BEGIN(14),COUNTER_BEGIN_D(14),CLK_4,'0','0');
     COUNTER_BEGIN_D(14) <= ((EXP0_.EXP)
      OR (M(1) AND M(2) AND COUNTER_BEGIN(14).LFBK)
      OR (M(1) AND L(0) AND COUNTER_BEGIN(14).LFBK));
FDCPE_L0: FDCPE port map (L(0),L_D(0),CLK_4,'0','0');
     L_D(0) <= (NOT LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND
      NOT LOOP_CNT(3).LFBK AND NOT LOOP_CNT(4).LFBK);
FTCPE_LOOP_CNT0: FTCPE port map (LOOP_CNT(0),'1',CLK_4,'0','0');
FTCPE_LOOP_CNT1: FTCPE port map (LOOP_CNT(1),LOOP_CNT(0),CLK_4,'0','0');
FTCPE_LOOP_CNT2: FTCPE port map (LOOP_CNT(2),LOOP_CNT_T(2),CLK_4,'0','0');
     LOOP_CNT_T(2) <= (LOOP_CNT(0) AND LOOP_CNT(1).LFBK);
FTCPE_LOOP_CNT3: FTCPE port map (LOOP_CNT(3),LOOP_CNT_T(3),CLK_4,'0','0');
     LOOP_CNT_T(3) <= (LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND
      LOOP_CNT(2).LFBK);
FTCPE_LOOP_CNT4: FTCPE port map (LOOP_CNT(4),LOOP_CNT_T(4),CLK_4,'0','0');
     LOOP_CNT_T(4) <= (LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND
      LOOP_CNT(2).LFBK AND LOOP_CNT(3).LFBK);
FDCPE_M0: FDCPE port map (M(0),M_D(0),CLK_4,'0','0');
     M_D(0) <= ((LOOP_CNT(2).LFBK AND LOOP_CNT(4).LFBK)
      OR (LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK)
      OR (NOT LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND
      LOOP_CNT(4).LFBK)
      OR (NOT LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND
      NOT LOOP_CNT(3).LFBK));
FDCPE_M1: FDCPE port map (M(1),M_D(1),CLK_4,'0','0');
     M_D(1) <= ((EXP4_.EXP)
      OR (LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND
      NOT LOOP_CNT(3).LFBK)
      OR (LOOP_CNT(2).LFBK AND NOT LOOP_CNT(3).LFBK AND
      LOOP_CNT(4).LFBK)
      OR (LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND
      NOT LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK)
      OR (LOOP_CNT(0) AND NOT LOOP_CNT(1).LFBK AND
      LOOP_CNT(3).LFBK AND NOT LOOP_CNT(4).LFBK));
FDCPE_M2: FDCPE port map (M(2),M_D(2),CLK_4,'0','0');
     M_D(2) <= ((NOT LOOP_CNT(0) AND NOT LOOP_CNT(2).LFBK AND
      NOT LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK)
      OR (LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND
      LOOP_CNT(3).LFBK AND NOT LOOP_CNT(4).LFBK)
      OR (NOT LOOP_CNT(1).LFBK AND NOT LOOP_CNT(2).LFBK AND
      NOT LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);