********** Mapped Logic ********** |
FDCPE_Q0: FDCPE port map (Q(0),D(0),CLK,NOT CLRB,'0'); |
FDCPE_Q1: FDCPE port map (Q(1),D(1),CLK,NOT CLRB,'0'); |
FDCPE_Q2: FDCPE port map (Q(2),D(2),CLK,NOT CLRB,'0'); |
FDCPE_Q3: FDCPE port map (Q(3),D(3),CLK,NOT CLRB,'0'); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |