Design Name | SYRS_FF |
Device, Speed (SpeedFile Version) | XC95108, -10 (3.0) |
Date Created | Sun May 02 07:29:35 2010 |
Created By | Timing Report Generator: version J.30 |
Copyright | Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Min. Clock Period | 9.000 ns. |
Max. Clock Frequency (fSYSTEM) | 111.111 MHz. |
Limited by Clock Pulse Width for CLK | |
Clock to Setup (tCYC) | 9.000 ns. |
Setup to Clock at the Pad (tSU) | 6.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 6.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 9.0 | 2 | 2 |
AUTO_TS_P2P | 0.0 | 6.0 | 2 | 2 |
AUTO_TS_P2F | 0.0 | 8.5 | 5 | 5 |
AUTO_TS_F2P | 0.0 | 3.5 | 2 | 2 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
Q.Q to Q.D | 0.000 | 9.000 | -9.000 |
Q.Q to QB.D | 0.000 | 9.000 | -9.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
CLK to Q | 0.000 | 6.000 | -6.000 |
CLK to QB | 0.000 | 6.000 | -6.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
R to Q.D | 0.000 | 8.500 | -8.500 |
R to QB.D | 0.000 | 8.500 | -8.500 |
S to Q.D | 0.000 | 8.500 | -8.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
Q.Q to Q | 0.000 | 3.500 | -3.500 |
QB.Q to QB | 0.000 | 3.500 | -3.500 |
Clock | fEXT (MHz) | Reason |
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CLK | 111.111 | Limited by Clock Pulse Width for CLK |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
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R | 6.000 | 0.000 |
S | 6.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
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Q | 6.000 |
QB | 6.000 |
Source | Destination | Delay |
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Q.Q | Q.D | 9.000 |
Q.Q | QB.D | 9.000 |
Source Pad | Destination Pad | Delay |
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