********** Mapped Logic ********** |
FTCPE_BUFFER0: FTCPE port map (BUFFER(0),'1',CLK,'0','0'); |
FTCPE_BUFFER1: FTCPE port map (BUFFER(1),BUFFER(0).LFBK,CLK,'0','0'); |
FTCPE_BUFFER2: FTCPE port map (BUFFER(2),BUFFER_T(2),CLK,'0','0');
BUFFER_T(2) <= (BUFFER(0) AND BUFFER(1)); |
FTCPE_BUFFER3: FTCPE port map (BUFFER(3),BUFFER_T(3),CLK,'0','0');
BUFFER_T(3) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK); |
FTCPE_BUFFER4: FTCPE port map (BUFFER(4),BUFFER_T(4),CLK,'0','0');
BUFFER_T(4) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK); |
FTCPE_BUFFER5: FTCPE port map (BUFFER(5),BUFFER_T(5),CLK,'0','0');
BUFFER_T(5) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK); |
FTCPE_BUFFER6: FTCPE port map (BUFFER(6),BUFFER_T(6),CLK,'0','0');
BUFFER_T(6) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK); |
FTCPE_BUFFER7: FTCPE port map (BUFFER(7),BUFFER_T(7),CLK,'0','0');
BUFFER_T(7) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK); |
FTCPE_BUFFER8: FTCPE port map (BUFFER(8),BUFFER_T(8),CLK,'0','0');
BUFFER_T(8) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK); |
FTCPE_BUFFER9: FTCPE port map (BUFFER(9),BUFFER_T(9),CLK,'0','0');
BUFFER_T(9) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK); |
FTCPE_BUFFER10: FTCPE port map (BUFFER(10),BUFFER_T(10),CLK,'0','0');
BUFFER_T(10) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK); |
FTCPE_BUFFER11: FTCPE port map (BUFFER(11),BUFFER_T(11),CLK,'0','0');
BUFFER_T(11) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK); |
FTCPE_BUFFER12: FTCPE port map (BUFFER(12),BUFFER_T(12),CLK,'0','0');
BUFFER_T(12) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK AND BUFFER(11).LFBK); |
FTCPE_BUFFER13: FTCPE port map (BUFFER(13),BUFFER_T(13),CLK,'0','0');
BUFFER_T(13) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK AND BUFFER(11).LFBK AND BUFFER(12).LFBK); |
FTCPE_BUFFER14: FTCPE port map (BUFFER(14),BUFFER_T(14),CLK,'0','0');
BUFFER_T(14) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK AND BUFFER(11).LFBK AND BUFFER(12).LFBK AND BUFFER(13).LFBK); |
FTCPE_BUFFER15: FTCPE port map (BUFFER(15),BUFFER_T(15),CLK,'0','0');
BUFFER_T(15) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK AND BUFFER(11).LFBK AND BUFFER(12).LFBK AND BUFFER(13).LFBK AND BUFFER(14).LFBK); |
FTCPE_BUFFER16: FTCPE port map (BUFFER(16),BUFFER_T(16),CLK,'0','0');
BUFFER_T(16) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK AND BUFFER(11).LFBK AND BUFFER(12).LFBK AND BUFFER(13).LFBK AND BUFFER(14).LFBK AND BUFFER(15).LFBK); |
FTCPE_BUFFER17: FTCPE port map (BUFFER(17),BUFFER_T(17),CLK,'0','0');
BUFFER_T(17) <= (BUFFER(0) AND BUFFER(1) AND BUFFER(2).LFBK AND BUFFER(3).LFBK AND BUFFER(4).LFBK AND BUFFER(5).LFBK AND BUFFER(6).LFBK AND BUFFER(7).LFBK AND BUFFER(8).LFBK AND BUFFER(9).LFBK AND BUFFER(10).LFBK AND BUFFER(11).LFBK AND BUFFER(12).LFBK AND BUFFER(13).LFBK AND BUFFER(14).LFBK AND BUFFER(15).LFBK AND BUFFER(16).LFBK); |
FTCPE_BUFFER18: FTCPE port map (BUFFER(18),BUFFER_T(18),CLK,'0','0');
BUFFER_T(18) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9)); |
FTCPE_BUFFER19: FTCPE port map (BUFFER(19),BUFFER_T(19),CLK,'0','0');
BUFFER_T(19) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND BUFFER(18).LFBK); |
FTCPE_BUFFER20: FTCPE port map (BUFFER(20),BUFFER_T(20),CLK,'0','0');
BUFFER_T(20) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND BUFFER(18).LFBK AND BUFFER(19).LFBK); |
FTCPE_BUFFER21: FTCPE port map (BUFFER(21),BUFFER_T(21),CLK,'0','0');
BUFFER_T(21) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND BUFFER(18).LFBK AND BUFFER(19).LFBK AND BUFFER(20).LFBK); |
FTCPE_BUFFER22: FTCPE port map (BUFFER(22),BUFFER_T(22),CLK,'0','0');
BUFFER_T(22) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND BUFFER(18).LFBK AND BUFFER(19).LFBK AND BUFFER(20).LFBK AND BUFFER(21).LFBK); |
FDCPE_LED0: FDCPE port map (LED(0),LED_D(0),CLK,'0','0');
LED_D(0) <= (NOT STATUS(0).LFBK AND NOT STATUS(1).LFBK AND NOT STATUS(2).LFBK); |
FDCPE_LED1: FDCPE port map (LED(1),LED_D(1),CLK,'0','0');
LED_D(1) <= (STATUS(0).LFBK AND NOT STATUS(1).LFBK AND NOT STATUS(2).LFBK); |
FDCPE_LED2: FDCPE port map (LED(2),LED_D(2),CLK,'0','0');
LED_D(2) <= (NOT STATUS(0).LFBK AND STATUS(1).LFBK AND NOT STATUS(2).LFBK); |
FDCPE_LED3: FDCPE port map (LED(3),LED_D(3),CLK,'0','0');
LED_D(3) <= (STATUS(0).LFBK AND STATUS(1).LFBK AND NOT STATUS(2).LFBK); |
FDCPE_LED4: FDCPE port map (LED(4),LED_D(4),CLK,'0','0');
LED_D(4) <= (NOT STATUS(0).LFBK AND NOT STATUS(1).LFBK AND STATUS(2).LFBK); |
FDCPE_LED5: FDCPE port map (LED(5),LED_D(5),CLK,'0','0');
LED_D(5) <= (STATUS(0).LFBK AND NOT STATUS(1).LFBK AND STATUS(2).LFBK); |
FDCPE_LED6: FDCPE port map (LED(6),LED_D(6),CLK,'0','0');
LED_D(6) <= (NOT STATUS(0).LFBK AND STATUS(1).LFBK AND STATUS(2).LFBK); |
FDCPE_LED7: FDCPE port map (LED(7),LED_D(7),CLK,'0','0');
LED_D(7) <= (STATUS(0).LFBK AND STATUS(1).LFBK AND STATUS(2).LFBK); |
FTCPE_STATUS0: FTCPE port map (STATUS(0),STATUS_T(0),CLK,'0','0');
STATUS_T(0) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND BUFFER(18).LFBK AND BUFFER(19).LFBK AND BUFFER(20).LFBK AND BUFFER(21).LFBK AND BUFFER(22).LFBK); |
FTCPE_STATUS1: FTCPE port map (STATUS(1),STATUS_T(1),CLK,'0','0');
STATUS_T(1) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND STATUS(0).LFBK AND BUFFER(18).LFBK AND BUFFER(19).LFBK AND BUFFER(20).LFBK AND BUFFER(21).LFBK AND BUFFER(22).LFBK); |
FTCPE_STATUS2: FTCPE port map (STATUS(2),STATUS_T(2),CLK,'0','0');
STATUS_T(2) <= (BUFFER(0) AND BUFFER(10) AND BUFFER(11) AND BUFFER(12) AND BUFFER(13) AND BUFFER(14) AND BUFFER(15) AND BUFFER(16) AND BUFFER(17) AND BUFFER(1) AND BUFFER(2) AND BUFFER(3) AND BUFFER(4) AND BUFFER(5) AND BUFFER(6) AND BUFFER(7) AND BUFFER(8) AND BUFFER(9) AND STATUS(0).LFBK AND BUFFER(18).LFBK AND BUFFER(19).LFBK AND BUFFER(20).LFBK AND BUFFER(21).LFBK AND BUFFER(22).LFBK AND STATUS(1).LFBK); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |