cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: LCD_TEST                            Date:  4-24-2010,  3:56PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
36 /108 ( 33%) 149 /540  ( 28%) 54 /216 ( 25%)   32 /108 ( 30%) 12 /69  ( 17%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          15/18       28/36       28          55/90       7/12
FB2           6/18       11/36       11          47/90       4/12
FB3          15/18       15/36       15          47/90       0/12
FB4           0/18        0/36        0           0/90       0/11
FB5           0/18        0/36        0           0/90       0/11
FB6           0/18        0/36        0           0/90       0/11
             -----       -----                   -----       -----     
             36/108      54/216                 149/540     11/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :    11      63
Output        :   10          10    |  GCK/IO           :     1       3
Bidirectional :    1           1    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     12          12

** Power Data **

There are 36 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB1,
   because too many function block product terms are required. Buffering output
   signal LCD_DATA<2> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2,
   because too many function block product terms are required. Buffering output
   signal LCD_DATA<4> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB2,
   because too many function block product terms are required. Buffering output
   signal LCD_DATA<6> to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 11 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
LCD_DATA<3>         13    8     FB1_2   1    I/O     O       STD  FAST RESET
LCD_DATA<2>         1     1     FB1_3   2    I/O     O       STD  FAST 
LCD_DATA<1>         11    8     FB1_5   3    I/O     O       STD  FAST RESET
LCD_DATA<0>         15    8     FB1_6   4    I/O     O       STD  FAST RESET
EN                  1     16    FB1_8   5    I/O     I/O     STD  FAST RESET
RW                  0     0     FB1_9   6    I/O     O       STD  FAST 
RS                  6     8     FB1_11  7    I/O     O       STD  FAST RESET
LCD_DATA<7>         6     8     FB2_14  81   I/O     O       STD  FAST RESET
LCD_DATA<6>         1     1     FB2_15  82   I/O     O       STD  FAST 
LCD_DATA<5>         12    8     FB2_16  83   I/O     O       STD  FAST RESET
LCD_DATA<4>         1     1     FB2_17  84   I/O     O       STD  FAST 

** 25 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
COUNTER<9>          1     9     FB1_10  STD  RESET
COUNTER<8>          1     8     FB1_12  STD  RESET
COUNTER<15>         1     15    FB1_13  STD  RESET
COUNTER<14>         1     14    FB1_14  STD  RESET
COUNTER<13>         1     13    FB1_15  STD  RESET
COUNTER<12>         1     12    FB1_16  STD  RESET
COUNTER<11>         1     11    FB1_17  STD  RESET
COUNTER<10>         1     10    FB1_18  STD  RESET
LCD_DATA<4>_BUFR    15    8     FB2_1   STD  RESET
LCD_DATA<6>_BUFR    12    8     FB2_4   STD  RESET
LCD_DATA<2>_BUFR    15    8     FB3_1   STD  RESET
COUNTER<7>          1     7     FB3_4   STD  RESET
COUNTER<6>          1     6     FB3_5   STD  RESET
COUNTER<5>          1     5     FB3_6   STD  RESET
COUNTER<4>          1     4     FB3_7   STD  RESET
COUNTER<3>          1     3     FB3_8   STD  RESET
COUNTER<2>          1     2     FB3_9   STD  RESET
COUNTER<1>          1     1     FB3_10  STD  RESET
COUNTER<0>          0     0     FB3_11  STD  RESET
CURRENT<4>          3     7     FB3_12  STD  RESET
CURRENT<3>          3     6     FB3_13  STD  RESET
CURRENT<0>          4     7     FB3_14  STD  RESET
CURRENT<5>          5     7     FB3_15  STD  RESET
CURRENT<2>          5     7     FB3_16  STD  RESET
CURRENT<1>          5     6     FB3_17  STD  RESET

** 1 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
CLK                 FB1_12  9    GCK/I/O GCK

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               28/8
Number of signals used by logic mapping into function block:  28
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB1_1         (b)     (b)
LCD_DATA<3>          13       8<-   0   0     FB1_2   1     I/O     O
LCD_DATA<2>           1       0   \/2   2     FB1_3   2     I/O     O
(unused)              0       0   \/5   0     FB1_4         (b)     (b)
LCD_DATA<1>          11       7<- \/1   0     FB1_5   3     I/O     O
LCD_DATA<0>          15      10<-   0   0     FB1_6   4     I/O     O
(unused)              0       0   /\5   0     FB1_7         (b)     (b)
EN                    1       0   /\4   0     FB1_8   5     I/O     I/O
RW                    0       0     0   5     FB1_9   6     I/O     O
COUNTER<9>            1       0   \/1   3     FB1_10        (b)     (b)
RS                    6       1<-   0   0     FB1_11  7     I/O     O
COUNTER<8>            1       0     0   4     FB1_12  9     GCK/I/O GCK
COUNTER<15>           1       0     0   4     FB1_13        (b)     (b)
COUNTER<14>           1       0     0   4     FB1_14  10    GCK/I/O (b)
COUNTER<13>           1       0     0   4     FB1_15  11    I/O     (b)
COUNTER<12>           1       0     0   4     FB1_16  12    GCK/I/O (b)
COUNTER<11>           1       0     0   4     FB1_17  13    I/O     (b)
COUNTER<10>           1       0   \/3   1     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK_LOW.LFBK      11: COUNTER<3>        20: CURRENT<2> 
  2: COUNTER<0>        12: COUNTER<4>        21: CURRENT<3> 
  3: COUNTER<10>.LFBK  13: COUNTER<5>        22: CURRENT<4> 
  4: COUNTER<11>.LFBK  14: COUNTER<6>        23: CURRENT<5> 
  5: COUNTER<12>.LFBK  15: COUNTER<7>        24: LCD_DATA<2>_BUFR 
  6: COUNTER<13>.LFBK  16: COUNTER<8>.LFBK   25: LCD_DATA_0.LFBK 
  7: COUNTER<14>.LFBK  17: COUNTER<9>.LFBK   26: LCD_DATA_1.LFBK 
  8: COUNTER<15>.LFBK  18: CURRENT<0>        27: LCD_DATA_3.LFBK 
  9: COUNTER<1>        19: CURRENT<1>        28: RS_OBUF.LFBK 
 10: COUNTER<2>       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LCD_DATA<3>          X................XXXXXX...X............. 8       8
LCD_DATA<2>          .......................X................ 1       1
LCD_DATA<1>          X................XXXXXX..X.............. 8       8
LCD_DATA<0>          X................XXXXXX.X............... 8       8
EN                   .XXXXXXXXXXXXXXXX....................... 16      16
RW                   ........................................ 0       0
COUNTER<9>           .X......XXXXXXXX........................ 9       9
RS                   X................XXXXXX....X............ 8       8
COUNTER<8>           .X......XXXXXXX......................... 8       8
COUNTER<15>          .XXXXXX.XXXXXXXXX....................... 15      15
COUNTER<14>          .XXXXX..XXXXXXXXX....................... 14      14
COUNTER<13>          .XXXX...XXXXXXXXX....................... 13      13
COUNTER<12>          .XXX....XXXXXXXXX....................... 12      12
COUNTER<11>          .XX.....XXXXXXXXX....................... 11      11
COUNTER<10>          .X......XXXXXXXXX....................... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               11/25
Number of signals used by logic mapping into function block:  11
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
LCD_DATA<4>_BUFR     15      10<-   0   0     FB2_1         (b)     (b)
(unused)              0       0   /\5   0     FB2_2   71    I/O     (b)
(unused)              0       0   \/5   0     FB2_3   72    I/O     (b)
LCD_DATA<6>_BUFR     12       7<-   0   0     FB2_4         (b)     (b)
(unused)              0       0   /\2   3     FB2_5   74    GSR/I/O (b)
(unused)              0       0     0   5     FB2_6   75    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   76    GTS/I/O 
(unused)              0       0     0   5     FB2_9   77    GTS/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  79    I/O     
(unused)              0       0     0   5     FB2_12  80    I/O     
(unused)              0       0   \/1   4     FB2_13        (b)     (b)
LCD_DATA<7>           6       1<-   0   0     FB2_14  81    I/O     O
LCD_DATA<6>           1       0   \/3   1     FB2_15  82    I/O     O
LCD_DATA<5>          12       7<-   0   0     FB2_16  83    I/O     O
LCD_DATA<4>           1       0   /\4   0     FB2_17  84    I/O     O
(unused)              0       0   \/5   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CURRENT<0>         5: CURRENT<4>              9: LCD_DATA<6>_BUFR.LFBK 
  2: CURRENT<1>         6: CURRENT<5>             10: LCD_DATA_5.LFBK 
  3: CURRENT<2>         7: EN.PIN                 11: LCD_DATA_7.LFBK 
  4: CURRENT<3>         8: LCD_DATA<4>_BUFR.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LCD_DATA<4>_BUFR     XXXXXXXX................................ 8       8
LCD_DATA<6>_BUFR     XXXXXXX.X............................... 8       8
LCD_DATA<7>          XXXXXXX...X............................. 8       8
LCD_DATA<6>          ........X............................... 1       1
LCD_DATA<5>          XXXXXXX..X.............................. 8       8
LCD_DATA<4>          .......X................................ 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               15/21
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
LCD_DATA<2>_BUFR     15      10<-   0   0     FB3_1         (b)     (b)
(unused)              0       0   /\5   0     FB3_2   14    I/O     (b)
(unused)              0       0     0   5     FB3_3   15    I/O     
COUNTER<7>            1       0     0   4     FB3_4         (b)     (b)
COUNTER<6>            1       0     0   4     FB3_5   17    I/O     (b)
COUNTER<5>            1       0     0   4     FB3_6   18    I/O     (b)
COUNTER<4>            1       0     0   4     FB3_7         (b)     (b)
COUNTER<3>            1       0     0   4     FB3_8   19    I/O     (b)
COUNTER<2>            1       0     0   4     FB3_9   20    I/O     (b)
COUNTER<1>            1       0     0   4     FB3_10        (b)     (b)
COUNTER<0>            0       0     0   5     FB3_11  21    I/O     (b)
CURRENT<4>            3       0     0   2     FB3_12  23    I/O     (b)
CURRENT<3>            3       0     0   2     FB3_13        (b)     (b)
CURRENT<0>            4       0     0   1     FB3_14  24    I/O     (b)
CURRENT<5>            5       0     0   0     FB3_15  25    I/O     (b)
CURRENT<2>            5       0     0   0     FB3_16  26    I/O     (b)
CURRENT<1>            5       0     0   0     FB3_17  31    I/O     (b)
(unused)              0       0   \/5   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: COUNTER<0>.LFBK    6: COUNTER<5>.LFBK   11: CURRENT<3>.LFBK 
  2: COUNTER<1>.LFBK    7: COUNTER<6>.LFBK   12: CURRENT<4>.LFBK 
  3: COUNTER<2>.LFBK    8: CURRENT<0>.LFBK   13: CURRENT<5>.LFBK 
  4: COUNTER<3>.LFBK    9: CURRENT<1>.LFBK   14: EN.PIN 
  5: COUNTER<4>.LFBK   10: CURRENT<2>.LFBK   15: LCD_DATA<2>_BUFR.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LCD_DATA<2>_BUFR     .......XXXXXXXX......................... 8       8
COUNTER<7>           XXXXXXX................................. 7       7
COUNTER<6>           XXXXXX.................................. 6       6
COUNTER<5>           XXXXX................................... 5       5
COUNTER<4>           XXXX.................................... 4       4
COUNTER<3>           XXX..................................... 3       3
COUNTER<2>           XX...................................... 2       2
COUNTER<1>           X....................................... 1       1
COUNTER<0>           ........................................ 0       0
CURRENT<4>           .......XXXXXXX.......................... 7       7
CURRENT<3>           .......XXXX.XX.......................... 6       6
CURRENT<0>           .......XXXXXXX.......................... 7       7
CURRENT<5>           .......XXXXXXX.......................... 7       7
CURRENT<2>           .......XXXXXXX.......................... 7       7
CURRENT<1>           .......XX.XXXX.......................... 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   57    I/O     
(unused)              0       0     0   5     FB4_3   58    I/O     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   61    I/O     
(unused)              0       0     0   5     FB4_6   62    I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   63    I/O     
(unused)              0       0     0   5     FB4_9   65    I/O     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  66    I/O     
(unused)              0       0     0   5     FB4_12  67    I/O     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  68    I/O     
(unused)              0       0     0   5     FB4_15  69    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  70    I/O     
(unused)              0       0     0   5     FB4_18        (b)     
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   32    I/O     
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     
(unused)              0       0     0   5     FB5_9   37    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
(unused)              0       0     0   5     FB6_2   45    I/O     
(unused)              0       0     0   5     FB6_3   46    I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   47    I/O     
(unused)              0       0     0   5     FB6_6   48    I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   50    I/O     
(unused)              0       0     0   5     FB6_9   51    I/O     
(unused)              0       0     0   5     FB6_10        (b)     
(unused)              0       0     0   5     FB6_11  52    I/O     
(unused)              0       0     0   5     FB6_12  53    I/O     
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  54    I/O     
(unused)              0       0     0   5     FB6_15  55    I/O     
(unused)              0       0     0   5     FB6_16        (b)     
(unused)              0       0     0   5     FB6_17  56    I/O     
(unused)              0       0     0   5     FB6_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_COUNTER0: FTCPE port map (COUNTER(0),'1',CLK,'0','0');

FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER(0).LFBK,CLK,'0','0');

FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
COUNTER_T(2) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK);

FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
COUNTER_T(3) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK);

FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
COUNTER_T(4) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK);

FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
COUNTER_T(5) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK);

FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
COUNTER_T(6) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK);

FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
COUNTER_T(7) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK);

FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
COUNTER_T(8) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7));

FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
COUNTER_T(9) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8).LFBK);

FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
COUNTER_T(10) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8).LFBK AND COUNTER(9).LFBK);

FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
COUNTER_T(11) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(10).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK);

FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
COUNTER_T(12) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK);

FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
COUNTER_T(13) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK);

FTCPE_COUNTER14: FTCPE port map (COUNTER(14),COUNTER_T(14),CLK,'0','0');
COUNTER_T(14) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(13).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK);

FTCPE_COUNTER15: FTCPE port map (COUNTER(15),COUNTER_T(15),CLK,'0','0');
COUNTER_T(15) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(13).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK);

FDCPE_CURRENT0: FDCPE port map (CURRENT(0),CURRENT_D(0),EN.PIN,'0','0');
CURRENT_D(0) <= ((NOT CURRENT(0).LFBK AND NOT CURRENT(5).LFBK)
	OR (NOT CURRENT(0).LFBK AND NOT CURRENT(1).LFBK AND 
	NOT CURRENT(3).LFBK AND NOT CURRENT(4).LFBK)
	OR (NOT CURRENT(0).LFBK AND NOT CURRENT(3).LFBK AND 
	NOT CURRENT(2).LFBK AND NOT CURRENT(4).LFBK));

FDCPE_CURRENT1: FDCPE port map (CURRENT(1),CURRENT_D(1),EN.PIN,'0','0');
CURRENT_D(1) <= ((CURRENT(0).LFBK AND NOT CURRENT(1).LFBK AND 
	NOT CURRENT(5).LFBK)
	OR (NOT CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	NOT CURRENT(5).LFBK)
	OR (CURRENT(0).LFBK AND NOT CURRENT(1).LFBK AND 
	NOT CURRENT(3).LFBK AND NOT CURRENT(4).LFBK)
	OR (NOT CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	NOT CURRENT(3).LFBK AND NOT CURRENT(4).LFBK));

FTCPE_CURRENT2: FTCPE port map (CURRENT(2),CURRENT_T(2),EN.PIN,'0','0');
CURRENT_T(2) <= ((CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	NOT CURRENT(5).LFBK)
	OR (CURRENT(3).LFBK AND CURRENT(2).LFBK AND 
	CURRENT(5).LFBK)
	OR (CURRENT(2).LFBK AND CURRENT(5).LFBK AND 
	CURRENT(4).LFBK)
	OR (CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	NOT CURRENT(3).LFBK AND NOT CURRENT(4).LFBK));

FTCPE_CURRENT3: FTCPE port map (CURRENT(3),CURRENT_T(3),EN.PIN,'0','0');
CURRENT_T(3) <= ((CURRENT(3).LFBK AND CURRENT(5).LFBK)
	OR (CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	CURRENT(2).LFBK AND NOT CURRENT(5).LFBK));

FTCPE_CURRENT4: FTCPE port map (CURRENT(4),CURRENT_T(4),EN.PIN,'0','0');
CURRENT_T(4) <= ((CURRENT(5).LFBK AND CURRENT(4).LFBK)
	OR (CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	CURRENT(3).LFBK AND CURRENT(2).LFBK AND NOT CURRENT(5).LFBK));

FDCPE_CURRENT5: FDCPE port map (CURRENT(5),CURRENT_D(5),EN.PIN,'0','0');
CURRENT_D(5) <= ((NOT CURRENT(0).LFBK AND NOT CURRENT(3).LFBK AND 
	CURRENT(5).LFBK AND NOT CURRENT(4).LFBK)
	OR (NOT CURRENT(1).LFBK AND NOT CURRENT(3).LFBK AND 
	CURRENT(5).LFBK AND NOT CURRENT(4).LFBK)
	OR (NOT CURRENT(3).LFBK AND NOT CURRENT(2).LFBK AND 
	CURRENT(5).LFBK AND NOT CURRENT(4).LFBK)
	OR (CURRENT(0).LFBK AND CURRENT(1).LFBK AND 
	CURRENT(3).LFBK AND CURRENT(2).LFBK AND NOT CURRENT(5).LFBK AND 
	CURRENT(4).LFBK));

FTCPE_EN: FTCPE port map (EN,EN_T,CLK,'0','0');
EN_T <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(13).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(15).LFBK);





















FDCPE_LCD_DATA0: FDCPE port map (LCD_DATA(0),LCD_DATA_D(0),CLK_LOW.LFBK,'0','0');
LCD_DATA_D(0) <= ((LCD_DATA_1.EXP)
	OR (EXP2_.EXP)
	OR (NOT CURRENT(0) AND CURRENT(2) AND CURRENT(1) AND 
	NOT CURRENT(5))
	OR (NOT CURRENT(0) AND NOT CURRENT(2) AND NOT CURRENT(3) AND 
	NOT CURRENT(4))
	OR (CURRENT(2) AND CURRENT(1) AND CURRENT(5) AND 
	NOT LCD_DATA_0.LFBK)
	OR (NOT CURRENT(0) AND NOT CURRENT(3) AND NOT CURRENT(4) AND 
	NOT CURRENT(5) AND NOT LCD_DATA_0.LFBK));

FDCPE_LCD_DATA1: FDCPE port map (LCD_DATA(1),LCD_DATA_D(1),CLK_LOW.LFBK,'0','0');
LCD_DATA_D(1) <= ((EXP1_.EXP)
	OR (CURRENT(3) AND CURRENT(5) AND LCD_DATA_1.LFBK)
	OR (CURRENT(4) AND CURRENT(5) AND LCD_DATA_1.LFBK)
	OR (CURRENT(0) AND CURRENT(2) AND CURRENT(1) AND 
	NOT CURRENT(3) AND NOT CURRENT(5)));

FDCPE_LCD_DATA2_BUFR: FDCPE port map (LCD_DATA(2)_BUFR,LCD_DATA_D(2)_BUFR,EN.PIN,'0','0');
LCD_DATA_D(2)_BUFR <= ((EXP8_.EXP)
	OR (EXP9_.EXP)
	OR (LCD_DATA(2)_BUFR.LFBK AND CURRENT(3).LFBK AND 
	CURRENT(5).LFBK)
	OR (LCD_DATA(2)_BUFR.LFBK AND CURRENT(5).LFBK AND 
	CURRENT(4).LFBK)
	OR (LCD_DATA(2)_BUFR.LFBK AND NOT CURRENT(0).LFBK AND 
	NOT CURRENT(1).LFBK AND NOT CURRENT(3).LFBK)
	OR (NOT CURRENT(0).LFBK AND NOT CURRENT(3).LFBK AND 
	NOT CURRENT(2).LFBK AND NOT CURRENT(5).LFBK));


LCD_DATA(2) <= LCD_DATA(2)_BUFR;

FDCPE_LCD_DATA3: FDCPE port map (LCD_DATA(3),LCD_DATA_D(3),CLK_LOW.LFBK,'0','0');
LCD_DATA_D(3) <= ((EXP0_.EXP)
	OR (CURRENT(3) AND CURRENT(5) AND LCD_DATA_3.LFBK)
	OR (CURRENT(4) AND CURRENT(5) AND LCD_DATA_3.LFBK)
	OR (CURRENT(0) AND CURRENT(1) AND CURRENT(5) AND 
	LCD_DATA_3.LFBK)
	OR (NOT CURRENT(0) AND NOT CURRENT(1) AND CURRENT(3) AND 
	NOT CURRENT(4) AND NOT CURRENT(5)));

FDCPE_LCD_DATA4_BUFR: FDCPE port map (LCD_DATA(4)_BUFR,LCD_DATA_D(4)_BUFR,EN.PIN,'0','0');
LCD_DATA_D(4)_BUFR <= ((EXP3_.EXP)
	OR (EXP7_.EXP)
	OR (CURRENT(3) AND CURRENT(5) AND LCD_DATA(4)_BUFR.LFBK)
	OR (CURRENT(4) AND CURRENT(5) AND LCD_DATA(4)_BUFR.LFBK)
	OR (NOT CURRENT(2) AND CURRENT(3) AND NOT CURRENT(4) AND 
	NOT CURRENT(5))
	OR (NOT CURRENT(2) AND NOT CURRENT(1) AND NOT CURRENT(3) AND 
	NOT CURRENT(4) AND CURRENT(5)));


LCD_DATA(4) <= LCD_DATA(4)_BUFR.LFBK;

FDCPE_LCD_DATA5: FDCPE port map (LCD_DATA(5),LCD_DATA_D(5),EN.PIN,'0','0');
LCD_DATA_D(5) <= ((_10_.EXP)
	OR (_9_.EXP)
	OR (CURRENT(3) AND CURRENT(5) AND NOT LCD_DATA_5.LFBK)
	OR (CURRENT(4) AND CURRENT(5) AND NOT LCD_DATA_5.LFBK)
	OR (CURRENT(0) AND CURRENT(2) AND CURRENT(4) AND 
	NOT CURRENT(5))
	OR (CURRENT(0) AND CURRENT(3) AND CURRENT(4) AND 
	NOT CURRENT(5)));


LCD_DATA(6) <= LCD_DATA(6)_BUFR.LFBK;

FDCPE_LCD_DATA6_BUFR: FDCPE port map (LCD_DATA(6)_BUFR,LCD_DATA_D(6)_BUFR,EN.PIN,'0','0');
LCD_DATA_D(6)_BUFR <= ((EXP4_.EXP)
	OR (EXP5_.EXP)
	OR (CURRENT(3) AND CURRENT(5) AND NOT LCD_DATA(6)_BUFR.LFBK)
	OR (CURRENT(2) AND CURRENT(1) AND CURRENT(5) AND 
	NOT LCD_DATA(6)_BUFR.LFBK)
	OR (NOT CURRENT(1) AND CURRENT(3) AND NOT CURRENT(4) AND 
	NOT CURRENT(5))
	OR (NOT CURRENT(1) AND NOT CURRENT(4) AND NOT CURRENT(5) AND 
	NOT LCD_DATA(6)_BUFR.LFBK));

FDCPE_LCD_DATA7: FDCPE port map (LCD_DATA(7),LCD_DATA_D(7),EN.PIN,'0','0');
LCD_DATA_D(7) <= ((EXP6_.EXP)
	OR (CURRENT(3) AND CURRENT(5) AND LCD_DATA_7.LFBK)
	OR (CURRENT(4) AND CURRENT(5) AND LCD_DATA_7.LFBK)
	OR (CURRENT(0) AND CURRENT(2) AND CURRENT(1) AND 
	CURRENT(5) AND LCD_DATA_7.LFBK)
	OR (CURRENT(0) AND CURRENT(2) AND NOT CURRENT(1) AND 
	NOT CURRENT(3) AND CURRENT(4) AND NOT CURRENT(5)));

FTCPE_RS: FTCPE port map (RS,RS_T,CLK_LOW.LFBK,'0','0');
RS_T <= ((COUNTER(9).EXP)
	OR (CURRENT(0) AND CURRENT(2) AND NOT CURRENT(1) AND 
	NOT CURRENT(3) AND CURRENT(4) AND NOT CURRENT(5) AND RS_OBUF.LFBK)
	OR (NOT CURRENT(0) AND CURRENT(2) AND CURRENT(1) AND 
	NOT CURRENT(3) AND CURRENT(4) AND NOT CURRENT(5) AND NOT RS_OBUF.LFBK)
	OR (NOT CURRENT(0) AND CURRENT(2) AND CURRENT(1) AND 
	NOT CURRENT(3) AND NOT CURRENT(4) AND CURRENT(5) AND RS_OBUF.LFBK)
	OR (NOT CURRENT(0) AND NOT CURRENT(2) AND NOT CURRENT(1) AND 
	NOT CURRENT(3) AND NOT CURRENT(4) AND NOT CURRENT(5) AND RS_OBUF.LFBK));


RW <= '0';

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


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  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
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 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
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 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 LCD_DATA<3>                      43 TIE                           
  2 LCD_DATA<2>                      44 TIE                           
  3 LCD_DATA<1>                      45 TIE                           
  4 LCD_DATA<0>                      46 TIE                           
  5 EN                               47 TIE                           
  6 RW                               48 TIE                           
  7 RS                               49 GND                           
  8 GND                              50 TIE                           
  9 CLK                              51 TIE                           
 10 TIE                              52 TIE                           
 11 TIE                              53 TIE                           
 12 TIE                              54 TIE                           
 13 TIE                              55 TIE                           
 14 TIE                              56 TIE                           
 15 TIE                              57 TIE                           
 16 GND                              58 TIE                           
 17 TIE                              59 TDO                           
 18 TIE                              60 GND                           
 19 TIE                              61 TIE                           
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 TIE                           
 24 TIE                              66 TIE                           
 25 TIE                              67 TIE                           
 26 TIE                              68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 TIE                              73 VCC                           
 32 TIE                              74 TIE                           
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 LCD_DATA<7>                   
 40 TIE                              82 LCD_DATA<6>                   
 41 TIE                              83 LCD_DATA<5>                   
 42 GND                              84 LCD_DATA<4>                   


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25