********** Mapped Logic ********** |
FDCPE_Q0: FDCPE port map (Q(0),DATA,CLK,NOT CLRB,'0'); |
FDCPE_Q1: FDCPE port map (Q(1),Q_0.LFBK,CLK,NOT CLRB,'0'); |
FDCPE_Q2: FDCPE port map (Q(2),Q_1.LFBK,CLK,NOT CLRB,'0'); |
FDCPE_Q3: FDCPE port map (Q(3),Q_2.LFBK,CLK,NOT CLRB,'0'); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |