cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: CPLD_MCU_RW                         Date:  4-24-2010,  4:52PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
33 /108 ( 31%) 82  /540  ( 15%) 55 /216 ( 25%)   25 /108 ( 23%) 27 /69  ( 39%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          15/18       18/36       18          33/90       4/12
FB2           4/18        5/36        5           8/90       4/12
FB3          14/18       32/36       32          41/90       8/12
FB4           0/18        0/36        0           0/90       0/11
FB5           0/18        0/36        0           0/90       0/11
FB6           0/18        0/36        0           0/90       0/11
             -----       -----                   -----       -----     
             33/108      55/216                  82/540     16/69 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   11          11    |  I/O              :    27      63
Output        :    8           8    |  GCK/IO           :     0       3
Bidirectional :    8           8    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     27          27

** Power Data **

There are 33 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 16 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
DATA_PORT<3>        2     2     FB1_2   1    I/O     I/O     STD  FAST 
DATA_PORT<2>        2     2     FB1_3   2    I/O     I/O     STD  FAST 
DATA_PORT<1>        2     2     FB1_5   3    I/O     I/O     STD  FAST 
DATA_PORT<0>        2     2     FB1_6   4    I/O     I/O     STD  FAST 
DATA_PORT<7>        2     2     FB2_14  81   I/O     I/O     STD  FAST 
DATA_PORT<6>        2     2     FB2_15  82   I/O     I/O     STD  FAST 
DATA_PORT<5>        2     2     FB2_16  83   I/O     I/O     STD  FAST 
DATA_PORT<4>        2     2     FB2_17  84   I/O     I/O     STD  FAST 
LED<7>              3     11    FB3_8   19   I/O     O       STD  FAST RESET
LED<6>              3     11    FB3_9   20   I/O     O       STD  FAST RESET
LED<5>              3     11    FB3_11  21   I/O     O       STD  FAST RESET
LED<4>              3     11    FB3_12  23   I/O     O       STD  FAST RESET
LED<3>              3     11    FB3_14  24   I/O     O       STD  FAST RESET
LED<2>              3     11    FB3_15  25   I/O     O       STD  FAST RESET
LED<1>              3     11    FB3_16  26   I/O     O       STD  FAST RESET
LED<0>              3     11    FB3_17  31   I/O     O       STD  FAST RESET

** 17 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
CONTROL_REG<7>      2     2     FB1_8   STD  RESET
CONTROL_REG<6>      2     2     FB1_9   STD  RESET
CONTROL_REG<5>      2     2     FB1_10  STD  RESET
CONTROL_REG<4>      2     2     FB1_11  STD  RESET
CONTROL_REG<3>      2     2     FB1_12  STD  RESET
CONTROL_REG<2>      2     2     FB1_13  STD  RESET
CONTROL_REG<1>      2     2     FB1_14  STD  RESET
CONTROL_REG<0>      2     2     FB1_15  STD  RESET
KEY_REG<7>          3     3     FB1_16  STD  RESET
KEY_REG<6>          3     3     FB1_17  STD  RESET
KEY_REG<5>          3     3     FB1_18  STD  RESET
Mtrien_KEY_REG      2     9     FB3_5   STD  RESET
KEY_REG<4>          3     3     FB3_6   STD  RESET
KEY_REG<3>          3     3     FB3_7   STD  RESET
KEY_REG<2>          3     3     FB3_10  STD  RESET
KEY_REG<1>          3     3     FB3_13  STD  RESET
KEY_REG<0>          3     3     FB3_18  STD  RESET

** 11 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
ALE                 FB1_15  11   I/O     I
WR                  FB3_5   17   I/O     I
RD                  FB3_6   18   I/O     I
KEY<7>              FB5_3   33   I/O     I
KEY<6>              FB5_5   34   I/O     I
KEY<5>              FB5_6   35   I/O     I
KEY<4>              FB5_8   36   I/O     I
KEY<3>              FB5_9   37   I/O     I
KEY<2>              FB5_11  39   I/O     I
KEY<1>              FB5_12  40   I/O     I
KEY<0>              FB5_14  41   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
DATA_PORT<3>          2       0     0   3     FB1_2   1     I/O     I/O
DATA_PORT<2>          2       0     0   3     FB1_3   2     I/O     I/O
(unused)              0       0     0   5     FB1_4         (b)     
DATA_PORT<1>          2       0     0   3     FB1_5   3     I/O     I/O
DATA_PORT<0>          2       0     0   3     FB1_6   4     I/O     I/O
(unused)              0       0     0   5     FB1_7         (b)     
CONTROL_REG<7>        2       0     0   3     FB1_8   5     I/O     (b)
CONTROL_REG<6>        2       0     0   3     FB1_9   6     I/O     (b)
CONTROL_REG<5>        2       0     0   3     FB1_10        (b)     (b)
CONTROL_REG<4>        2       0     0   3     FB1_11  7     I/O     (b)
CONTROL_REG<3>        2       0     0   3     FB1_12  9     GCK/I/O (b)
CONTROL_REG<2>        2       0     0   3     FB1_13        (b)     (b)
CONTROL_REG<1>        2       0     0   3     FB1_14  10    GCK/I/O (b)
CONTROL_REG<0>        2       0     0   3     FB1_15  11    I/O     I
KEY_REG<7>            3       0     0   2     FB1_16  12    GCK/I/O (b)
KEY_REG<6>            3       0     0   2     FB1_17  13    I/O     (b)
KEY_REG<5>            3       0     0   2     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ALE                7: KEY_REG<2>        13: DATA_PORT<4>.PIN 
  2: KEY<5>             8: KEY_REG<3>        14: DATA_PORT<3>.PIN 
  3: KEY<6>             9: Mtrien_KEY_REG    15: DATA_PORT<2>.PIN 
  4: KEY<7>            10: DATA_PORT<7>.PIN  16: DATA_PORT<1>.PIN 
  5: KEY_REG<0>        11: DATA_PORT<6>.PIN  17: DATA_PORT<0>.PIN 
  6: KEY_REG<1>        12: DATA_PORT<5>.PIN  18: RD 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DATA_PORT<3>         .......X.........X...................... 2       2
DATA_PORT<2>         ......X..........X...................... 2       2
DATA_PORT<1>         .....X...........X...................... 2       2
DATA_PORT<0>         ....X............X...................... 2       2
CONTROL_REG<7>       X........X.............................. 2       2
CONTROL_REG<6>       X.........X............................. 2       2
CONTROL_REG<5>       X..........X............................ 2       2
CONTROL_REG<4>       X...........X........................... 2       2
CONTROL_REG<3>       X............X.......................... 2       2
CONTROL_REG<2>       X.............X......................... 2       2
CONTROL_REG<1>       X..............X........................ 2       2
CONTROL_REG<0>       X...............X....................... 2       2
KEY_REG<7>           ...X....X........X...................... 3       3
KEY_REG<6>           ..X.....X........X...................... 3       3
KEY_REG<5>           .X......X........X...................... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               5/31
Number of signals used by logic mapping into function block:  5
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   71    I/O     
(unused)              0       0     0   5     FB2_3   72    I/O     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   74    GSR/I/O 
(unused)              0       0     0   5     FB2_6   75    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   76    GTS/I/O 
(unused)              0       0     0   5     FB2_9   77    GTS/I/O 
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  79    I/O     
(unused)              0       0     0   5     FB2_12  80    I/O     
(unused)              0       0     0   5     FB2_13        (b)     
DATA_PORT<7>          2       0     0   3     FB2_14  81    I/O     I/O
DATA_PORT<6>          2       0     0   3     FB2_15  82    I/O     I/O
DATA_PORT<5>          2       0     0   3     FB2_16  83    I/O     I/O
DATA_PORT<4>          2       0     0   3     FB2_17  84    I/O     I/O
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: KEY_REG<4>         3: KEY_REG<6>         5: RD 
  2: KEY_REG<5>         4: KEY_REG<7>       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DATA_PORT<7>         ...XX................................... 2       2
DATA_PORT<6>         ..X.X................................... 2       2
DATA_PORT<5>         .X..X................................... 2       2
DATA_PORT<4>         X...X................................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   14    I/O     
(unused)              0       0     0   5     FB3_3   15    I/O     
(unused)              0       0     0   5     FB3_4         (b)     
Mtrien_KEY_REG        2       0     0   3     FB3_5   17    I/O     I
KEY_REG<4>            3       0     0   2     FB3_6   18    I/O     I
KEY_REG<3>            3       0     0   2     FB3_7         (b)     (b)
LED<7>                3       0     0   2     FB3_8   19    I/O     O
LED<6>                3       0     0   2     FB3_9   20    I/O     O
KEY_REG<2>            3       0     0   2     FB3_10        (b)     (b)
LED<5>                3       0     0   2     FB3_11  21    I/O     O
LED<4>                3       0     0   2     FB3_12  23    I/O     O
KEY_REG<1>            3       0     0   2     FB3_13        (b)     (b)
LED<3>                3       0     0   2     FB3_14  24    I/O     O
LED<2>                3       0     0   2     FB3_15  25    I/O     O
LED<1>                3       0     0   2     FB3_16  26    I/O     O
LED<0>                3       0     0   2     FB3_17  31    I/O     O
KEY_REG<0>            3       0     0   2     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CONTROL_REG<0>    12: KEY<3>               23: DATA_PORT<7>.PIN 
  2: CONTROL_REG<1>    13: KEY<4>               24: DATA_PORT<6>.PIN 
  3: CONTROL_REG<2>    14: LED_REG<0>.LFBK      25: DATA_PORT<5>.PIN 
  4: CONTROL_REG<3>    15: LED_REG<1>.LFBK      26: DATA_PORT<4>.PIN 
  5: CONTROL_REG<4>    16: LED_REG<2>.LFBK      27: DATA_PORT<3>.PIN 
  6: CONTROL_REG<5>    17: LED_REG<3>.LFBK      28: DATA_PORT<2>.PIN 
  7: CONTROL_REG<6>    18: LED_REG<4>.LFBK      29: DATA_PORT<1>.PIN 
  8: CONTROL_REG<7>    19: LED_REG<5>.LFBK      30: DATA_PORT<0>.PIN 
  9: KEY<0>            20: LED_REG<6>.LFBK      31: RD 
 10: KEY<1>            21: LED_REG<7>.LFBK      32: WR 
 11: KEY<2>            22: Mtrien_KEY_REG.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
Mtrien_KEY_REG       XXXXXXXX......................X......... 9       9
KEY_REG<4>           ............X........X........X......... 3       3
KEY_REG<3>           ...........X.........X........X......... 3       3
LED<7>               XXXXXXXX............X.X........X........ 11      11
LED<6>               XXXXXXXX...........X...X.......X........ 11      11
KEY_REG<2>           ..........X..........X........X......... 3       3
LED<5>               XXXXXXXX..........X.....X......X........ 11      11
LED<4>               XXXXXXXX.........X.......X.....X........ 11      11
KEY_REG<1>           .........X...........X........X......... 3       3
LED<3>               XXXXXXXX........X.........X....X........ 11      11
LED<2>               XXXXXXXX.......X...........X...X........ 11      11
LED<1>               XXXXXXXX......X.............X..X........ 11      11
LED<0>               XXXXXXXX.....X...............X.X........ 11      11
KEY_REG<0>           ........X............X........X......... 3       3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   57    I/O     
(unused)              0       0     0   5     FB4_3   58    I/O     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   61    I/O     
(unused)              0       0     0   5     FB4_6   62    I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   63    I/O     
(unused)              0       0     0   5     FB4_9   65    I/O     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  66    I/O     
(unused)              0       0     0   5     FB4_12  67    I/O     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  68    I/O     
(unused)              0       0     0   5     FB4_15  69    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  70    I/O     
(unused)              0       0     0   5     FB4_18        (b)     
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   32    I/O     
(unused)              0       0     0   5     FB5_3   33    I/O     I
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     I
(unused)              0       0     0   5     FB5_6   35    I/O     I
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     I
(unused)              0       0     0   5     FB5_9   37    I/O     I
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     I
(unused)              0       0     0   5     FB5_12  40    I/O     I
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     I
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
(unused)              0       0     0   5     FB6_2   45    I/O     
(unused)              0       0     0   5     FB6_3   46    I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   47    I/O     
(unused)              0       0     0   5     FB6_6   48    I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   50    I/O     
(unused)              0       0     0   5     FB6_9   51    I/O     
(unused)              0       0     0   5     FB6_10        (b)     
(unused)              0       0     0   5     FB6_11  52    I/O     
(unused)              0       0     0   5     FB6_12  53    I/O     
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  54    I/O     
(unused)              0       0     0   5     FB6_15  55    I/O     
(unused)              0       0     0   5     FB6_16        (b)     
(unused)              0       0     0   5     FB6_17  56    I/O     
(unused)              0       0     0   5     FB6_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_CONTROL_REG0: FDCPE port map (CONTROL_REG(0),DATA_PORT(0).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG1: FDCPE port map (CONTROL_REG(1),DATA_PORT(1).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG2: FDCPE port map (CONTROL_REG(2),DATA_PORT(2).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG3: FDCPE port map (CONTROL_REG(3),DATA_PORT(3).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG4: FDCPE port map (CONTROL_REG(4),DATA_PORT(4).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG5: FDCPE port map (CONTROL_REG(5),DATA_PORT(5).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG6: FDCPE port map (CONTROL_REG(6),DATA_PORT(6).PIN,NOT ALE,'0','0');

FDCPE_CONTROL_REG7: FDCPE port map (CONTROL_REG(7),DATA_PORT(7).PIN,NOT ALE,'0','0');


DATA_PORT_I(0) <= KEY_REG(0);
DATA_PORT(0) <= DATA_PORT_I(0) when DATA_PORT_OE(0) = '1' else 'Z';
DATA_PORT_OE(0) <= NOT RD;


DATA_PORT_I(1) <= KEY_REG(1);
DATA_PORT(1) <= DATA_PORT_I(1) when DATA_PORT_OE(1) = '1' else 'Z';
DATA_PORT_OE(1) <= NOT RD;


DATA_PORT_I(2) <= KEY_REG(2);
DATA_PORT(2) <= DATA_PORT_I(2) when DATA_PORT_OE(2) = '1' else 'Z';
DATA_PORT_OE(2) <= NOT RD;


DATA_PORT_I(3) <= KEY_REG(3);
DATA_PORT(3) <= DATA_PORT_I(3) when DATA_PORT_OE(3) = '1' else 'Z';
DATA_PORT_OE(3) <= NOT RD;


DATA_PORT_I(4) <= KEY_REG(4);
DATA_PORT(4) <= DATA_PORT_I(4) when DATA_PORT_OE(4) = '1' else 'Z';
DATA_PORT_OE(4) <= NOT RD;


DATA_PORT_I(5) <= KEY_REG(5);
DATA_PORT(5) <= DATA_PORT_I(5) when DATA_PORT_OE(5) = '1' else 'Z';
DATA_PORT_OE(5) <= NOT RD;


DATA_PORT_I(6) <= KEY_REG(6);
DATA_PORT(6) <= DATA_PORT_I(6) when DATA_PORT_OE(6) = '1' else 'Z';
DATA_PORT_OE(6) <= NOT RD;


DATA_PORT_I(7) <= KEY_REG(7);
DATA_PORT(7) <= DATA_PORT_I(7) when DATA_PORT_OE(7) = '1' else 'Z';
DATA_PORT_OE(7) <= NOT RD;

FDCPE_KEY_REG0: FDCPE port map (KEY_REG(0),KEY(0),NOT RD,'0','0');

FDCPE_KEY_REG1: FDCPE port map (KEY_REG(1),KEY(1),NOT RD,'0','0');

FDCPE_KEY_REG2: FDCPE port map (KEY_REG(2),KEY(2),NOT RD,'0','0');

FDCPE_KEY_REG3: FDCPE port map (KEY_REG(3),KEY(3),NOT RD,'0','0');

FDCPE_KEY_REG4: FDCPE port map (KEY_REG(4),KEY(4),NOT RD,'0','0');

FDCPE_KEY_REG5: FDCPE port map (KEY_REG(5),KEY(5),NOT RD,'0','0');

FDCPE_KEY_REG6: FDCPE port map (KEY_REG(6),KEY(6),NOT RD,'0','0');

FDCPE_KEY_REG7: FDCPE port map (KEY_REG(7),KEY(7),NOT RD,'0','0');

FTCPE_LED0: FTCPE port map (LED(0),LED_T(0),NOT WR,'0','0');
LED_T(0) <= ((DATA_PORT(0).PIN AND CONTROL_REG(0) AND 
	NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	NOT LED_REG(0).LFBK)
	OR (NOT DATA_PORT(0).PIN AND CONTROL_REG(0) AND 
	NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	LED_REG(0).LFBK));

FTCPE_LED1: FTCPE port map (LED(1),LED_T(1),NOT WR,'0','0');
LED_T(1) <= ((CONTROL_REG(0) AND DATA_PORT(1).PIN AND 
	NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	NOT LED_REG(1).LFBK)
	OR (CONTROL_REG(0) AND NOT DATA_PORT(1).PIN AND 
	NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	LED_REG(1).LFBK));

FTCPE_LED2: FTCPE port map (LED(2),LED_T(2),NOT WR,'0','0');
LED_T(2) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND 
	DATA_PORT(2).PIN AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	NOT LED_REG(2).LFBK)
	OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND 
	NOT DATA_PORT(2).PIN AND NOT CONTROL_REG(2) AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	LED_REG(2).LFBK));

FTCPE_LED3: FTCPE port map (LED(3),LED_T(3),NOT WR,'0','0');
LED_T(3) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	DATA_PORT(3).PIN AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND 
	NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND NOT LED_REG(3).LFBK)
	OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT DATA_PORT(3).PIN AND NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND 
	NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND LED_REG(3).LFBK));

FTCPE_LED4: FTCPE port map (LED(4),LED_T(4),NOT WR,'0','0');
LED_T(4) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND DATA_PORT(4).PIN AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	NOT LED_REG(4).LFBK)
	OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT DATA_PORT(4).PIN AND NOT CONTROL_REG(4) AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	LED_REG(4).LFBK));

FTCPE_LED5: FTCPE port map (LED(5),LED_T(5),NOT WR,'0','0');
LED_T(5) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND DATA_PORT(5).PIN AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	NOT LED_REG(5).LFBK)
	OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT DATA_PORT(5).PIN AND 
	NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	LED_REG(5).LFBK));

FTCPE_LED6: FTCPE port map (LED(6),LED_T(6),NOT WR,'0','0');
LED_T(6) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND 
	DATA_PORT(6).PIN AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	NOT LED_REG(6).LFBK)
	OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND 
	NOT DATA_PORT(6).PIN AND NOT CONTROL_REG(6) AND NOT CONTROL_REG(7) AND 
	LED_REG(6).LFBK));

FTCPE_LED7: FTCPE port map (LED(7),LED_T(7),NOT WR,'0','0');
LED_T(7) <= ((CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND 
	DATA_PORT(7).PIN AND NOT CONTROL_REG(7) AND NOT LED_REG(7).LFBK)
	OR (CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND 
	NOT DATA_PORT(7).PIN AND NOT CONTROL_REG(7) AND LED_REG(7).LFBK));

FDCPE_Mtrien_KEY_REG: FDCPE port map (Mtrien_KEY_REG,Mtrien_KEY_REG_D,NOT RD,'0','0');
Mtrien_KEY_REG_D <= (NOT CONTROL_REG(0) AND NOT CONTROL_REG(1) AND NOT CONTROL_REG(2) AND 
	NOT CONTROL_REG(3) AND NOT CONTROL_REG(4) AND NOT CONTROL_REG(5) AND NOT CONTROL_REG(6) AND 
	NOT CONTROL_REG(7));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 DATA_PORT<3>                     43 TIE                           
  2 DATA_PORT<2>                     44 TIE                           
  3 DATA_PORT<1>                     45 TIE                           
  4 DATA_PORT<0>                     46 TIE                           
  5 TIE                              47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 TIE                              51 TIE                           
 10 TIE                              52 TIE                           
 11 ALE                              53 TIE                           
 12 TIE                              54 TIE                           
 13 TIE                              55 TIE                           
 14 TIE                              56 TIE                           
 15 TIE                              57 TIE                           
 16 GND                              58 TIE                           
 17 WR                               59 TDO                           
 18 RD                               60 GND                           
 19 LED<7>                           61 TIE                           
 20 LED<6>                           62 TIE                           
 21 LED<5>                           63 TIE                           
 22 VCC                              64 VCC                           
 23 LED<4>                           65 TIE                           
 24 LED<3>                           66 TIE                           
 25 LED<2>                           67 TIE                           
 26 LED<1>                           68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 LED<0>                           73 VCC                           
 32 TIE                              74 TIE                           
 33 KEY<7>                           75 TIE                           
 34 KEY<6>                           76 TIE                           
 35 KEY<5>                           77 TIE                           
 36 KEY<4>                           78 VCC                           
 37 KEY<3>                           79 TIE                           
 38 VCC                              80 TIE                           
 39 KEY<2>                           81 DATA_PORT<7>                  
 40 KEY<1>                           82 DATA_PORT<6>                  
 41 KEY<0>                           83 DATA_PORT<5>                  
 42 GND                              84 DATA_PORT<4>                  


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25