cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: CPLD_MUSIC                          Date:  4-28-2010,  4:14PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
83 /108 ( 77%) 286 /540  ( 53%) 132/216 ( 61%)   50 /108 ( 46%) 13 /69  ( 19%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          16/18       30/36       30          55/90       4/12
FB2          16/18       23/36       23          33/90       4/12
FB3          13/18       32/36       32          55/90       1/12
FB4          12/18        8/36        8          76/90       0/11
FB5          16/18       22/36       22          47/90       0/11
FB6          10/18       17/36       17          20/90       0/11
             -----       -----                   -----       -----     
             83/108     132/216                 286/540      9/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :    12      63
Output        :    1           1    |  GCK/IO           :     1       3
Bidirectional :    8           8    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     13          13

** Power Data **

There are 83 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 9 Outputs **

Signal                                    Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                      Pts   Inps          No.  Type    Use     Mode Rate State
DATA_PORT<3>                              2     2     FB1_2   1    I/O     I/O     STD  FAST 
DATA_PORT<2>                              2     2     FB1_3   2    I/O     I/O     STD  FAST 
DATA_PORT<1>                              2     2     FB1_5   3    I/O     I/O     STD  FAST 
DATA_PORT<0>                              2     2     FB1_6   4    I/O     I/O     STD  FAST 
DATA_PORT<7>                              2     2     FB2_14  81   I/O     I/O     STD  FAST 
DATA_PORT<6>                              2     2     FB2_15  82   I/O     I/O     STD  FAST 
DATA_PORT<5>                              2     2     FB2_16  83   I/O     I/O     STD  FAST 
DATA_PORT<4>                              2     2     FB2_17  84   I/O     I/O     STD  FAST 
MUSIC_OUT                                 1     11    FB3_8   19   I/O     O       STD  FAST RESET

** 74 Buried Nodes **

Signal                                    Total Total Loc     Pwr  Reg Init
Name                                      Pts   Inps          Mode State
DATA_REG<6>                               3     11    FB1_1   STD  RESET
ADDRESS_REG<4>                            2     2     FB1_7   STD  RESET
ADDRESS_REG<3>                            2     2     FB1_8   STD  RESET
ADDRESS_REG<2>                            2     2     FB1_9   STD  RESET
ADDRESS_REG<1>                            2     2     FB1_10  STD  RESET
DATA_REG<7>                               3     11    FB1_11  STD  RESET
DATA_REG<5>                               3     11    FB1_12  STD  RESET
DATA_REG<4>                               3     11    FB1_13  STD  RESET
COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_RSTF  3     8     FB1_14  STD  
COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_SETF    8     8     FB1_15  STD  
COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_RSTF    8     8     FB1_17  STD  
COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_SETF    8     8     FB1_18  STD  
ACK_REG<3>                                1     1     FB2_3   STD  
ACK_REG<2>                                1     1     FB2_4   STD  
ACK_REG<1>                                1     1     FB2_5   STD  
ACK_REG<7>                                2     2     FB2_6   STD  RESET
ACK_REG<6>                                2     2     FB2_7   STD  RESET
ACK_REG<5>                                2     2     FB2_8   STD  RESET
ACK_REG<4>                                2     2     FB2_9   STD  RESET
ACK_REG<0>                                2     2     FB2_10  STD  RESET
DATA_REG<3>                               3     11    FB2_11  STD  RESET
DATA_REG<2>                               3     11    FB2_12  STD  RESET
DATA_REG<1>                               3     11    FB2_13  STD  RESET
DATA_REG<0>                               3     11    FB2_18  STD  RESET
Mtrien_ACK_REG                            2     9     FB3_1   STD  RESET
COUNTER<0>                                2     13    FB3_7   STD  RESET
COUNTER<1>                                3     13    FB3_9   STD  RESET
COUNTER<10>                               3     13    FB3_10  STD  RESET
COUNTER<9>                                4     13    FB3_11  STD  RESET
COUNTER<2>                                4     13    FB3_12  STD  RESET
COUNTER<8>                                5     13    FB3_13  STD  RESET
COUNTER<3>                                5     13    FB3_14  STD  RESET
COUNTER<7>                                6     13    FB3_15  STD  RESET
COUNTER<4>                                6     13    FB3_16  STD  RESET
COUNTER<6>                                7     13    FB3_17  STD  RESET
COUNTER<5>                                7     13    FB3_18  STD  RESET
COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_RSTF    5     8     FB4_1   STD  
COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_SETF    6     8     FB4_6   STD  
COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_RSTF    6     8     FB4_7   STD  
COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_SETF    6     8     FB4_8   STD  

Signal                                    Total Total Loc     Pwr  Reg Init
Name                                      Pts   Inps          Mode State
COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_RSTF    6     8     FB4_9   STD  
COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_SETF    6     8     FB4_10  STD  
COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_SETF    6     8     FB4_12  STD  
COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_SETF    7     8     FB4_13  STD  
COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_RSTF    7     8     FB4_14  STD  
COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_RSTF    7     8     FB4_16  STD  
COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_RSTF    7     8     FB4_17  STD  
COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_SETF    7     8     FB4_18  STD  
CNT<1>                                    1     1     FB5_3   STD  RESET
CNT<0>                                    0     0     FB5_4   STD  RESET
CLK_1M                                    1     4     FB5_5   STD  RESET
CNT<3>                                    2     4     FB5_6   STD  RESET
CNT<2>                                    2     4     FB5_7   STD  RESET
COUNTER_BEGIN<3>                          2     2     FB5_8   STD  RESET
COUNTER_BEGIN<2>                          2     2     FB5_9   STD  RESET
COUNTER_BEGIN<1>                          2     2     FB5_10  STD  RESET
COUNTER_BEGIN<10>                         2     2     FB5_11  STD  RESET
COUNTER_BEGIN<0>                          2     2     FB5_12  STD  RESET
COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_SETF    5     8     FB5_13  STD  
COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_SETF    5     8     FB5_14  STD  
COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_RSTF    5     8     FB5_15  STD  
COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_RSTF    5     8     FB5_16  STD  
COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_SETF  5     8     FB5_17  STD  
COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_RSTF    6     8     FB5_18  STD  
ADDRESS_REG<7>                            2     2     FB6_9   STD  RESET
ADDRESS_REG<6>                            2     2     FB6_10  STD  RESET
ADDRESS_REG<5>                            2     2     FB6_11  STD  RESET
ADDRESS_REG<0>                            2     2     FB6_12  STD  RESET
COUNTER_BEGIN<9>                          2     2     FB6_13  STD  RESET
COUNTER_BEGIN<8>                          2     2     FB6_14  STD  RESET
COUNTER_BEGIN<7>                          2     2     FB6_15  STD  RESET
COUNTER_BEGIN<6>                          2     2     FB6_16  STD  RESET
COUNTER_BEGIN<5>                          2     2     FB6_17  STD  RESET
COUNTER_BEGIN<4>                          2     2     FB6_18  STD  RESET

** 4 Inputs **

Signal                                    Loc     Pin  Pin     Pin     
Name                                              No.  Type    Use     
CLK                                       FB1_12  9    GCK/I/O GCK
ALE                                       FB1_15  11   I/O     I
WR                                        FB3_5   17   I/O     I
RD                                        FB3_6   18   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               30/6
Number of signals used by logic mapping into function block:  30
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
DATA_REG<6>           3       0   /\2   0     FB1_1         (b)     (b)
DATA_PORT<3>          2       0     0   3     FB1_2   1     I/O     I/O
DATA_PORT<2>          2       0     0   3     FB1_3   2     I/O     I/O
(unused)              0       0     0   5     FB1_4         (b)     
DATA_PORT<1>          2       0     0   3     FB1_5   3     I/O     I/O
DATA_PORT<0>          2       0     0   3     FB1_6   4     I/O     I/O
ADDRESS_REG<4>        2       0     0   3     FB1_7         (b)     (b)
ADDRESS_REG<3>        2       0     0   3     FB1_8   5     I/O     (b)
ADDRESS_REG<2>        2       0     0   3     FB1_9   6     I/O     (b)
ADDRESS_REG<1>        2       0     0   3     FB1_10        (b)     (b)
DATA_REG<7>           3       0     0   2     FB1_11  7     I/O     (b)
DATA_REG<5>           3       0     0   2     FB1_12  9     GCK/I/O GCK
DATA_REG<4>           3       0   \/1   1     FB1_13        (b)     (b)
COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_RSTF
                      3       1<- \/3   0     FB1_14  10    GCK/I/O (b)
COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_SETF
                      8       3<-   0   0     FB1_15  11    I/O     I
(unused)              0       0   \/4   1     FB1_16  12    GCK/I/O (b)
COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_RSTF
                      8       4<- \/1   0     FB1_17  13    I/O     (b)
COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_SETF
                      8       3<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ACK_REG<0>           11: ADDRESS_REG<6>    21: DATA_REG<7>.LFBK 
  2: ACK_REG<1>           12: ADDRESS_REG<7>    22: DATA_PORT<7>.PIN 
  3: ACK_REG<2>           13: ALE               23: DATA_PORT<6>.PIN 
  4: ACK_REG<3>           14: DATA_REG<0>       24: DATA_PORT<5>.PIN 
  5: ADDRESS_REG<0>       15: DATA_REG<1>       25: DATA_PORT<4>.PIN 
  6: ADDRESS_REG<1>.LFBK  16: DATA_REG<2>       26: DATA_PORT<3>.PIN 
  7: ADDRESS_REG<2>.LFBK  17: DATA_REG<3>       27: DATA_PORT<2>.PIN 
  8: ADDRESS_REG<3>.LFBK  18: DATA_REG<4>.LFBK  28: DATA_PORT<1>.PIN 
  9: ADDRESS_REG<4>.LFBK  19: DATA_REG<5>.LFBK  29: RD 
 10: ADDRESS_REG<5>       20: DATA_REG<6>.LFBK  30: WR 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DATA_REG<6>          ....XXXXXXXX.......X..X......X.......... 11      11
DATA_PORT<3>         ...X........................X........... 2       2
DATA_PORT<2>         ..X.........................X........... 2       2
DATA_PORT<1>         .X..........................X........... 2       2
DATA_PORT<0>         X...........................X........... 2       2
ADDRESS_REG<4>       ............X...........X............... 2       2
ADDRESS_REG<3>       ............X............X.............. 2       2
ADDRESS_REG<2>       ............X.............X............. 2       2
ADDRESS_REG<1>       ............X..............X............ 2       2
DATA_REG<7>          ....XXXXXXXX........XX.......X.......... 11      11
DATA_REG<5>          ....XXXXXXXX......X....X.....X.......... 11      11
DATA_REG<4>          ....XXXXXXXX.....X......X....X.......... 11      11
COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_RSTF 
                     .............XXXXXXXX................... 8       8
COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_SETF 
                     .............XXXXXXXX................... 8       8
COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_RSTF 
                     .............XXXXXXXX................... 8       8
COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_SETF 
                     .............XXXXXXXX................... 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               23/13
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   71    I/O     
ACK_REG<3>            1       0     0   4     FB2_3   72    I/O     (b)
ACK_REG<2>            1       0     0   4     FB2_4         (b)     (b)
ACK_REG<1>            1       0     0   4     FB2_5   74    GSR/I/O (b)
ACK_REG<7>            2       0     0   3     FB2_6   75    I/O     (b)
ACK_REG<6>            2       0     0   3     FB2_7         (b)     (b)
ACK_REG<5>            2       0     0   3     FB2_8   76    GTS/I/O (b)
ACK_REG<4>            2       0     0   3     FB2_9   77    GTS/I/O (b)
ACK_REG<0>            2       0     0   3     FB2_10        (b)     (b)
DATA_REG<3>           3       0     0   2     FB2_11  79    I/O     (b)
DATA_REG<2>           3       0     0   2     FB2_12  80    I/O     (b)
DATA_REG<1>           3       0     0   2     FB2_13        (b)     (b)
DATA_PORT<7>          2       0     0   3     FB2_14  81    I/O     I/O
DATA_PORT<6>          2       0     0   3     FB2_15  82    I/O     I/O
DATA_PORT<5>          2       0     0   3     FB2_16  83    I/O     I/O
DATA_PORT<4>          2       0     0   3     FB2_17  84    I/O     I/O
DATA_REG<0>           3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ACK_REG<4>         9: ADDRESS_REG<4>    17: Mtrien_ACK_REG 
  2: ACK_REG<5>        10: ADDRESS_REG<5>    18: DATA_PORT<3>.PIN 
  3: ACK_REG<6>        11: ADDRESS_REG<6>    19: DATA_PORT<2>.PIN 
  4: ACK_REG<7>        12: ADDRESS_REG<7>    20: DATA_PORT<1>.PIN 
  5: ADDRESS_REG<0>    13: DATA_REG<0>.LFBK  21: DATA_PORT<0>.PIN 
  6: ADDRESS_REG<1>    14: DATA_REG<1>.LFBK  22: RD 
  7: ADDRESS_REG<2>    15: DATA_REG<2>.LFBK  23: WR 
  8: ADDRESS_REG<3>    16: DATA_REG<3>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ACK_REG<3>           ................X....................... 1       1
ACK_REG<2>           ................X....................... 1       1
ACK_REG<1>           ................X....................... 1       1
ACK_REG<7>           ................X....X.................. 2       2
ACK_REG<6>           ................X....X.................. 2       2
ACK_REG<5>           ................X....X.................. 2       2
ACK_REG<4>           ................X....X.................. 2       2
ACK_REG<0>           ................X....X.................. 2       2
DATA_REG<3>          ....XXXXXXXX...X.X....X................. 11      11
DATA_REG<2>          ....XXXXXXXX..X...X...X................. 11      11
DATA_REG<1>          ....XXXXXXXX.X.....X..X................. 11      11
DATA_PORT<7>         ...X.................X.................. 2       2
DATA_PORT<6>         ..X..................X.................. 2       2
DATA_PORT<5>         .X...................X.................. 2       2
DATA_PORT<4>         X....................X.................. 2       2
DATA_REG<0>          ....XXXXXXXXX.......X.X................. 11      11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
Mtrien_ACK_REG        2       0   /\3   0     FB3_1         (b)     (b)
(unused)              0       0     0   5     FB3_2   14    I/O     
(unused)              0       0     0   5     FB3_3   15    I/O     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   17    I/O     I
(unused)              0       0     0   5     FB3_6   18    I/O     I
COUNTER<0>            2       0     0   3     FB3_7         (b)     (b)
MUSIC_OUT             1       0     0   4     FB3_8   19    I/O     O
COUNTER<1>            3       0     0   2     FB3_9   20    I/O     (b)
COUNTER<10>           3       0   \/1   1     FB3_10        (b)     (b)
COUNTER<9>            4       1<- \/2   0     FB3_11  21    I/O     (b)
COUNTER<2>            4       2<- \/3   0     FB3_12  23    I/O     (b)
COUNTER<8>            5       3<- \/3   0     FB3_13        (b)     (b)
COUNTER<3>            5       3<- \/3   0     FB3_14  24    I/O     (b)
COUNTER<7>            6       3<- \/2   0     FB3_15  25    I/O     (b)
COUNTER<4>            6       2<- \/1   0     FB3_16  26    I/O     (b)
COUNTER<6>            7       2<-   0   0     FB3_17  31    I/O     (b)
COUNTER<5>            7       3<- /\1   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ADDRESS_REG<0>    12: COUNTER<1>.LFBK    23: COUNTER_BEGIN<1> 
  2: ADDRESS_REG<1>    13: COUNTER<2>.LFBK    24: COUNTER_BEGIN<2> 
  3: ADDRESS_REG<2>    14: COUNTER<3>.LFBK    25: COUNTER_BEGIN<3> 
  4: ADDRESS_REG<3>    15: COUNTER<4>.LFBK    26: COUNTER_BEGIN<4> 
  5: ADDRESS_REG<4>    16: COUNTER<5>.LFBK    27: COUNTER_BEGIN<5> 
  6: ADDRESS_REG<5>    17: COUNTER<6>.LFBK    28: COUNTER_BEGIN<6> 
  7: ADDRESS_REG<6>    18: COUNTER<7>.LFBK    29: COUNTER_BEGIN<7> 
  8: ADDRESS_REG<7>    19: COUNTER<8>.LFBK    30: COUNTER_BEGIN<8> 
  9: CLK_1M            20: COUNTER<9>.LFBK    31: COUNTER_BEGIN<9> 
 10: COUNTER<0>.LFBK   21: COUNTER_BEGIN<0>   32: RD 
 11: COUNTER<10>.LFBK  22: COUNTER_BEGIN<10> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
Mtrien_ACK_REG       XXXXXXXX.......................X........ 9       9
COUNTER<0>           ........XXXXXXXXXXXXX................... 13      13
MUSIC_OUT            .........XXXXXXXXXXX.................... 11      11
COUNTER<1>           ........XXXXXXXXXXXX..X................. 13      13
COUNTER<10>          ........XXXXXXXXXXXX.X.................. 13      13
COUNTER<9>           ........XXXXXXXXXXXX..........X......... 13      13
COUNTER<2>           ........XXXXXXXXXXXX...X................ 13      13
COUNTER<8>           ........XXXXXXXXXXXX.........X.......... 13      13
COUNTER<3>           ........XXXXXXXXXXXX....X............... 13      13
COUNTER<7>           ........XXXXXXXXXXXX........X........... 13      13
COUNTER<4>           ........XXXXXXXXXXXX.....X.............. 13      13
COUNTER<6>           ........XXXXXXXXXXXX.......X............ 13      13
COUNTER<5>           ........XXXXXXXXXXXX......X............. 13      13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               8/28
Number of signals used by logic mapping into function block:  8
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_RSTF
                      5       2<- /\2   0     FB4_1         (b)     (b)
(unused)              0       0   /\2   3     FB4_2   57    I/O     (b)
(unused)              0       0     0   5     FB4_3   58    I/O     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0   \/5   0     FB4_5   61    I/O     (b)
COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_SETF
                      6       5<- \/4   0     FB4_6   62    I/O     (b)
COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_RSTF
                      6       4<- \/3   0     FB4_7         (b)     (b)
COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_SETF
                      6       3<- \/2   0     FB4_8   63    I/O     (b)
COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_RSTF
                      6       2<- \/1   0     FB4_9   65    I/O     (b)
COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_SETF
                      6       1<-   0   0     FB4_10        (b)     (b)
(unused)              0       0   \/5   0     FB4_11  66    I/O     (b)
COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_SETF
                      6       5<- \/4   0     FB4_12  67    I/O     (b)
COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_SETF
                      7       4<- \/2   0     FB4_13        (b)     (b)
COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_RSTF
                      7       2<-   0   0     FB4_14  68    I/O     (b)
(unused)              0       0   \/4   1     FB4_15  69    I/O     (b)
COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_RSTF
                      7       4<- \/2   0     FB4_16        (b)     (b)
COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_RSTF
                      7       2<-   0   0     FB4_17  70    I/O     (b)
COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_SETF
                      7       2<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DATA_REG<0>        4: DATA_REG<3>        7: DATA_REG<6> 
  2: DATA_REG<1>        5: DATA_REG<4>        8: DATA_REG<7> 
  3: DATA_REG<2>        6: DATA_REG<5>      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_RSTF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_SETF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_RSTF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_SETF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_RSTF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_SETF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_SETF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_SETF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_RSTF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_RSTF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_RSTF 
                     XXXXXXXX................................ 8       8
COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_SETF 
                     XXXXXXXX................................ 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               22/14
Number of signals used by logic mapping into function block:  22
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB5_1         (b)     (b)
(unused)              0       0     0   5     FB5_2   32    I/O     
CNT<1>                1       0     0   4     FB5_3   33    I/O     (b)
CNT<0>                0       0     0   5     FB5_4         (b)     (b)
CLK_1M                1       0     0   4     FB5_5   34    I/O     (b)
CNT<3>                2       0     0   3     FB5_6   35    I/O     (b)
CNT<2>                2       0     0   3     FB5_7         (b)     (b)
COUNTER_BEGIN<3>      2       0     0   3     FB5_8   36    I/O     (b)
COUNTER_BEGIN<2>      2       0     0   3     FB5_9   37    I/O     (b)
COUNTER_BEGIN<1>      2       0     0   3     FB5_10        (b)     (b)
COUNTER_BEGIN<10>     2       0     0   3     FB5_11  39    I/O     (b)
COUNTER_BEGIN<0>      2       0     0   3     FB5_12  40    I/O     (b)
COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_SETF
                      5       0     0   0     FB5_13        (b)     (b)
COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_SETF
                      5       0     0   0     FB5_14  41    I/O     (b)
COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_RSTF
                      5       0     0   0     FB5_15  43    I/O     (b)
COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_RSTF
                      5       0     0   0     FB5_16        (b)     (b)
COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_SETF
                      5       0     0   0     FB5_17  44    I/O     (b)
COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_RSTF
                      6       1<-   0   0     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CNT<0>.LFBK                                     9: COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_RSTF.LFBK  16: DATA_REG<1> 
  2: CNT<1>.LFBK                                    10: COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_SETF       17: DATA_REG<2> 
  3: CNT<2>.LFBK                                    11: COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_RSTF.LFBK  18: DATA_REG<3> 
  4: CNT<3>.LFBK                                    12: COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_SETF       19: DATA_REG<4> 
  5: COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_RSTF         13: COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_RSTF       20: DATA_REG<5> 
  6: COUNTER_BEGIN<0>/COUNTER_BEGIN<0>_SETF         14: COUNTER_BEGIN<3>/COUNTER_BEGIN<3>_SETF       21: DATA_REG<6> 
  7: COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_RSTF       15: DATA_REG<0>                                  22: DATA_REG<7> 
  8: COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_SETF.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CNT<1>               X....................................... 1       1
CNT<0>               ........................................ 0       0
CLK_1M               XXXX.................................... 4       4
CNT<3>               XXXX.................................... 4       4
CNT<2>               XXXX.................................... 4       4
COUNTER_BEGIN<3>     ............XX.......................... 2       2
COUNTER_BEGIN<2>     ..........XX............................ 2       2
COUNTER_BEGIN<1>     ........XX.............................. 2       2
COUNTER_BEGIN<10>    ......XX................................ 2       2
COUNTER_BEGIN<0>     ....XX.................................. 2       2
COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_SETF 
                     ..............XXXXXXXX.................. 8       8
COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_SETF 
                     ..............XXXXXXXX.................. 8       8
COUNTER_BEGIN<2>/COUNTER_BEGIN<2>_RSTF 
                     ..............XXXXXXXX.................. 8       8
COUNTER_BEGIN<1>/COUNTER_BEGIN<1>_RSTF 
                     ..............XXXXXXXX.................. 8       8
COUNTER_BEGIN<10>/COUNTER_BEGIN<10>_SETF 
                     ..............XXXXXXXX.................. 8       8
COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_RSTF 
                     ..............XXXXXXXX.................. 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               17/19
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
(unused)              0       0     0   5     FB6_2   45    I/O     
(unused)              0       0     0   5     FB6_3   46    I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   47    I/O     
(unused)              0       0     0   5     FB6_6   48    I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   50    I/O     
ADDRESS_REG<7>        2       0     0   3     FB6_9   51    I/O     (b)
ADDRESS_REG<6>        2       0     0   3     FB6_10        (b)     (b)
ADDRESS_REG<5>        2       0     0   3     FB6_11  52    I/O     (b)
ADDRESS_REG<0>        2       0     0   3     FB6_12  53    I/O     (b)
COUNTER_BEGIN<9>      2       0     0   3     FB6_13        (b)     (b)
COUNTER_BEGIN<8>      2       0     0   3     FB6_14  54    I/O     (b)
COUNTER_BEGIN<7>      2       0     0   3     FB6_15  55    I/O     (b)
COUNTER_BEGIN<6>      2       0     0   3     FB6_16        (b)     (b)
COUNTER_BEGIN<5>      2       0     0   3     FB6_17  56    I/O     (b)
COUNTER_BEGIN<4>      2       0     0   3     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ALE                                      7: COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_SETF  13: COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_SETF 
  2: COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_RSTF   8: COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_RSTF  14: DATA_PORT<7>.PIN 
  3: COUNTER_BEGIN<4>/COUNTER_BEGIN<4>_SETF   9: COUNTER_BEGIN<7>/COUNTER_BEGIN<7>_SETF  15: DATA_PORT<6>.PIN 
  4: COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_RSTF  10: COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_RSTF  16: DATA_PORT<5>.PIN 
  5: COUNTER_BEGIN<5>/COUNTER_BEGIN<5>_SETF  11: COUNTER_BEGIN<8>/COUNTER_BEGIN<8>_SETF  17: DATA_PORT<0>.PIN 
  6: COUNTER_BEGIN<6>/COUNTER_BEGIN<6>_RSTF  12: COUNTER_BEGIN<9>/COUNTER_BEGIN<9>_RSTF 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ADDRESS_REG<7>       X............X.......................... 2       2
ADDRESS_REG<6>       X.............X......................... 2       2
ADDRESS_REG<5>       X..............X........................ 2       2
ADDRESS_REG<0>       X...............X....................... 2       2
COUNTER_BEGIN<9>     ...........XX........................... 2       2
COUNTER_BEGIN<8>     .........XX............................. 2       2
COUNTER_BEGIN<7>     .......XX............................... 2       2
COUNTER_BEGIN<6>     .....XX................................. 2       2
COUNTER_BEGIN<5>     ...XX................................... 2       2
COUNTER_BEGIN<4>     .XX..................................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_ACK_REG0: FDCPE port map (ACK_REG(0),'1',NOT RD,'0','0');


ACK_REG(1) <= '0';


ACK_REG(2) <= '0';


ACK_REG(3) <= '0';

FDCPE_ACK_REG4: FDCPE port map (ACK_REG(4),'1',NOT RD,'0','0');

FDCPE_ACK_REG5: FDCPE port map (ACK_REG(5),'1',NOT RD,'0','0');

FDCPE_ACK_REG6: FDCPE port map (ACK_REG(6),'1',NOT RD,'0','0');

FDCPE_ACK_REG7: FDCPE port map (ACK_REG(7),'1',NOT RD,'0','0');

FDCPE_ADDRESS_REG0: FDCPE port map (ADDRESS_REG(0),DATA_PORT(0).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG1: FDCPE port map (ADDRESS_REG(1),DATA_PORT(1).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG2: FDCPE port map (ADDRESS_REG(2),DATA_PORT(2).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG3: FDCPE port map (ADDRESS_REG(3),DATA_PORT(3).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG4: FDCPE port map (ADDRESS_REG(4),DATA_PORT(4).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG5: FDCPE port map (ADDRESS_REG(5),DATA_PORT(5).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG6: FDCPE port map (ADDRESS_REG(6),DATA_PORT(6).PIN,NOT ALE,'0','0');

FDCPE_ADDRESS_REG7: FDCPE port map (ADDRESS_REG(7),DATA_PORT(7).PIN,NOT ALE,'0','0');

FTCPE_CLK_1M: FTCPE port map (CLK_1M,CLK_1M_T,CLK,'0','0');
CLK_1M_T <= (CNT(0).LFBK AND CNT(1).LFBK AND NOT CNT(2).LFBK AND 
	CNT(3).LFBK);

FTCPE_CNT0: FTCPE port map (CNT(0),'1',CLK,'0','0');

FTCPE_CNT1: FTCPE port map (CNT(1),CNT(0).LFBK,CLK,'0','0');

FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),CLK,'0','0');
CNT_T(2) <= ((CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK)
	OR (CNT(0).LFBK AND CNT(1).LFBK AND NOT CNT(3).LFBK));

FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),CLK,'0','0');
CNT_T(3) <= ((CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK)
	OR (CNT(0).LFBK AND CNT(1).LFBK AND CNT(3).LFBK));

FTCPE_COUNTER0: FTCPE port map (COUNTER(0),COUNTER_T(0),CLK_1M,'0','0');
COUNTER_T(0) <= (COUNTER_BEGIN(0) AND COUNTER(0).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND 
	COUNTER(10).LFBK);

FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER_T(1),CLK_1M,'0','0');
COUNTER_T(1) <= ((NOT COUNTER(0).LFBK)
	OR (COUNTER_BEGIN(1) AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(10).LFBK));

FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK_1M,'0','0');
COUNTER_T(2) <= ((COUNTER(9).EXP)
	OR (NOT COUNTER(0).LFBK));

FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK_1M,'0','0');
COUNTER_T(3) <= ((COUNTER(8).EXP)
	OR (NOT COUNTER(0).LFBK));

FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK_1M,'0','0');
COUNTER_T(4) <= ((COUNTER(7).EXP)
	OR (NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK)
	OR (NOT COUNTER(2).LFBK));

FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK_1M,'0','0');
COUNTER_T(5) <= ((Mtrien_ACK_REG.EXP)
	OR (NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK)
	OR (NOT COUNTER(2).LFBK));

FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK_1M,'0','0');
COUNTER_T(6) <= ((COUNTER(4).EXP)
	OR (COUNTER(5).EXP)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND NOT COUNTER(6).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND NOT COUNTER(7).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND NOT COUNTER(8).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND NOT COUNTER(9).LFBK));

FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK_1M,'0','0');
COUNTER_T(7) <= ((COUNTER(3).EXP)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND NOT COUNTER(7).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND NOT COUNTER(8).LFBK));

FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK_1M,'0','0');
COUNTER_T(8) <= ((COUNTER(2).EXP)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	NOT COUNTER(8).LFBK));

FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK_1M,'0','0');
COUNTER_T(9) <= ((COUNTER(10).EXP)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND NOT COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND NOT COUNTER(10).LFBK));

FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK_1M,'0','0');
COUNTER_T(10) <= ((NOT COUNTER_BEGIN(10) AND COUNTER(0).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND NOT COUNTER(10).LFBK));

FDCPE_COUNTER_BEGIN0: FDCPE port map (COUNTER_BEGIN(0),'0','0',COUNTER_BEGIN(0)/COUNTER_BEGIN(0)_RSTF,COUNTER_BEGIN(0)/COUNTER_BEGIN(0)_SETF);


COUNTER_BEGIN(0)/COUNTER_BEGIN(0)_SETF <= ((COUNTER_BEGIN(0)/COUNTER_BEGIN(0)_RSTF.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(4) AND DATA_REG(1) AND NOT DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND DATA_REG(1) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));


COUNTER_BEGIN(0)/COUNTER_BEGIN(0)_RSTF <= ((EXP1_.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));


COUNTER_BEGIN(1)/COUNTER_BEGIN(1)_SETF <= ((EXP3_.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));


COUNTER_BEGIN(1)/COUNTER_BEGIN(1)_RSTF <= ((NOT DATA_REG(2) AND DATA_REG(1) AND DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND DATA_REG(5) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN1: FDCPE port map (COUNTER_BEGIN(1),'0','0',COUNTER_BEGIN(1)/COUNTER_BEGIN(1)_RSTF.LFBK,COUNTER_BEGIN(1)/COUNTER_BEGIN(1)_SETF);

FDCPE_COUNTER_BEGIN2: FDCPE port map (COUNTER_BEGIN(2),'0','0',COUNTER_BEGIN(2)/COUNTER_BEGIN(2)_RSTF.LFBK,COUNTER_BEGIN(2)/COUNTER_BEGIN(2)_SETF);


COUNTER_BEGIN(2)/COUNTER_BEGIN(2)_RSTF <= ((DATA_REG(2) AND DATA_REG(4) AND DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND NOT DATA_REG(1) AND DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(4) AND NOT DATA_REG(5) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(5) AND DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));


COUNTER_BEGIN(2)/COUNTER_BEGIN(2)_SETF <= ((COUNTER_BEGIN(3)/COUNTER_BEGIN(3)_RSTF.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(5) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(1) AND DATA_REG(5) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(1) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));


COUNTER_BEGIN(3)/COUNTER_BEGIN(3)_RSTF <= ((COUNTER_BEGIN(3)/COUNTER_BEGIN(3)_SETF.EXP)
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND NOT DATA_REG(1) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN3: FDCPE port map (COUNTER_BEGIN(3),'0','0',COUNTER_BEGIN(3)/COUNTER_BEGIN(3)_RSTF,COUNTER_BEGIN(3)/COUNTER_BEGIN(3)_SETF);


COUNTER_BEGIN(3)/COUNTER_BEGIN(3)_SETF <= ((COUNTER_BEGIN(5)/COUNTER_BEGIN(5)_RSTF.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN4: FDCPE port map (COUNTER_BEGIN(4),'0','0',COUNTER_BEGIN(4)/COUNTER_BEGIN(4)_RSTF,COUNTER_BEGIN(4)/COUNTER_BEGIN(4)_SETF);


COUNTER_BEGIN(4)/COUNTER_BEGIN(4)_RSTF <= ((COUNTER_BEGIN(6)/COUNTER_BEGIN(6)_RSTF.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND DATA_REG(5) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND DATA_REG(1) AND DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND DATA_REG(5) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(4) AND NOT DATA_REG(1) AND NOT DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));


COUNTER_BEGIN(4)/COUNTER_BEGIN(4)_SETF <= ((DATA_REG(2) AND NOT DATA_REG(1) AND DATA_REG(5) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(5) AND DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN5: FDCPE port map (COUNTER_BEGIN(5),'0','0',COUNTER_BEGIN(5)/COUNTER_BEGIN(5)_RSTF,COUNTER_BEGIN(5)/COUNTER_BEGIN(5)_SETF);


COUNTER_BEGIN(5)/COUNTER_BEGIN(5)_SETF <= ((DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7))
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7))
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));


COUNTER_BEGIN(5)/COUNTER_BEGIN(5)_RSTF <= ((COUNTER_BEGIN(6)/COUNTER_BEGIN(6)_SETF.EXP)
	OR (DATA_REG(4) AND DATA_REG(0) AND NOT DATA_REG(3) AND 
	NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(4) AND DATA_REG(1) AND NOT DATA_REG(5) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN6: FDCPE port map (COUNTER_BEGIN(6),'0','0',COUNTER_BEGIN(6)/COUNTER_BEGIN(6)_RSTF,COUNTER_BEGIN(6)/COUNTER_BEGIN(6)_SETF);


COUNTER_BEGIN(6)/COUNTER_BEGIN(6)_RSTF <= ((EXP4_.EXP)
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(4) AND NOT DATA_REG(5) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));


COUNTER_BEGIN(6)/COUNTER_BEGIN(6)_SETF <= ((EXP2_.EXP)
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));


COUNTER_BEGIN(7)/COUNTER_BEGIN(7)_SETF <= ((DATA_REG(6).EXP)
	OR (COUNTER_BEGIN(8)/COUNTER_BEGIN(8)_RSTF.EXP)
	OR (DATA_REG(2) AND NOT DATA_REG(1) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (DATA_REG(1) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND 
	NOT DATA_REG(4).LFBK AND DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (NOT DATA_REG(2) AND DATA_REG(1) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND DATA_REG(4).LFBK AND DATA_REG(5).LFBK AND 
	NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK)
	OR (NOT DATA_REG(2) AND NOT DATA_REG(1) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND DATA_REG(4).LFBK AND NOT DATA_REG(5).LFBK AND 
	NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK)
	OR (NOT DATA_REG(2) AND NOT DATA_REG(1) AND NOT DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(4).LFBK AND NOT DATA_REG(5).LFBK AND 
	NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK));


COUNTER_BEGIN(7)/COUNTER_BEGIN(7)_RSTF <= ((COUNTER_BEGIN(8)/COUNTER_BEGIN(8)_SETF.EXP)
	OR (DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(1) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND DATA_REG(1) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN7: FDCPE port map (COUNTER_BEGIN(7),'0','0',COUNTER_BEGIN(7)/COUNTER_BEGIN(7)_RSTF,COUNTER_BEGIN(7)/COUNTER_BEGIN(7)_SETF);


COUNTER_BEGIN(8)/COUNTER_BEGIN(8)_RSTF <= ((EXP0_.EXP)
	OR (NOT DATA_REG(2) AND DATA_REG(0) AND NOT DATA_REG(3) AND 
	DATA_REG(4).LFBK AND NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK)
	OR (DATA_REG(2) AND NOT DATA_REG(1) AND NOT DATA_REG(0) AND 
	NOT DATA_REG(3) AND DATA_REG(4).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (NOT DATA_REG(2) AND DATA_REG(1) AND NOT DATA_REG(0) AND 
	NOT DATA_REG(3) AND DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (DATA_REG(1) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND 
	DATA_REG(4).LFBK AND DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK));


COUNTER_BEGIN(8)/COUNTER_BEGIN(8)_SETF <= ((COUNTER_BEGIN(1)/COUNTER_BEGIN(1)_SETF.EXP)
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(5) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(4) AND DATA_REG(1) AND NOT DATA_REG(5) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN8: FDCPE port map (COUNTER_BEGIN(8),'0','0',COUNTER_BEGIN(8)/COUNTER_BEGIN(8)_RSTF,COUNTER_BEGIN(8)/COUNTER_BEGIN(8)_SETF);

FDCPE_COUNTER_BEGIN9: FDCPE port map (COUNTER_BEGIN(9),'0','0',COUNTER_BEGIN(9)/COUNTER_BEGIN(9)_RSTF,COUNTER_BEGIN(9)/COUNTER_BEGIN(9)_SETF);


COUNTER_BEGIN(9)/COUNTER_BEGIN(9)_SETF <= ((COUNTER_BEGIN(10)/COUNTER_BEGIN(10)_RSTF.EXP)
	OR (DATA_REG(2) AND NOT DATA_REG(1) AND NOT DATA_REG(3) AND 
	DATA_REG(4).LFBK AND NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK)
	OR (DATA_REG(2) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND 
	DATA_REG(4).LFBK AND NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK)
	OR (DATA_REG(0) AND NOT DATA_REG(3) AND DATA_REG(4).LFBK AND 
	DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK)
	OR (NOT DATA_REG(2) AND DATA_REG(1) AND DATA_REG(0) AND 
	NOT DATA_REG(3) AND DATA_REG(4).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (NOT DATA_REG(2) AND NOT DATA_REG(1) AND NOT DATA_REG(0) AND 
	NOT DATA_REG(3) AND NOT DATA_REG(4).LFBK AND NOT DATA_REG(5).LFBK AND 
	NOT DATA_REG(6).LFBK AND NOT DATA_REG(7).LFBK));


COUNTER_BEGIN(9)/COUNTER_BEGIN(9)_RSTF <= ((EXP5_.EXP)
	OR (DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	DATA_REG(5) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND DATA_REG(5) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(4) AND DATA_REG(1) AND DATA_REG(5) AND 
	NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	NOT DATA_REG(5) AND DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));

FDCPE_COUNTER_BEGIN10: FDCPE port map (COUNTER_BEGIN(10),'0','0',COUNTER_BEGIN(10)/COUNTER_BEGIN(10)_RSTF,COUNTER_BEGIN(10)/COUNTER_BEGIN(10)_SETF.LFBK);


COUNTER_BEGIN(10)/COUNTER_BEGIN(10)_SETF <= ((DATA_REG(2) AND DATA_REG(5) AND NOT DATA_REG(3) AND 
	NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(1) AND DATA_REG(5) AND NOT DATA_REG(3) AND 
	NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(5) AND DATA_REG(0) AND NOT DATA_REG(3) AND 
	NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (DATA_REG(2) AND DATA_REG(4) AND DATA_REG(1) AND 
	DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND NOT DATA_REG(7))
	OR (NOT DATA_REG(2) AND NOT DATA_REG(4) AND NOT DATA_REG(1) AND 
	NOT DATA_REG(5) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND NOT DATA_REG(6) AND 
	NOT DATA_REG(7)));


COUNTER_BEGIN(10)/COUNTER_BEGIN(10)_RSTF <= ((DATA_REG(4).EXP)
	OR (NOT DATA_REG(2) AND DATA_REG(0) AND NOT DATA_REG(3) AND 
	DATA_REG(4).LFBK AND NOT DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (DATA_REG(1) AND NOT DATA_REG(0) AND NOT DATA_REG(3) AND 
	DATA_REG(4).LFBK AND NOT DATA_REG(5).LFBK AND NOT DATA_REG(6).LFBK AND 
	NOT DATA_REG(7).LFBK));


DATA_PORT_I(0) <= ACK_REG(0);
DATA_PORT(0) <= DATA_PORT_I(0) when DATA_PORT_OE(0) = '1' else 'Z';
DATA_PORT_OE(0) <= NOT RD;


DATA_PORT_I(1) <= ACK_REG(1);
DATA_PORT(1) <= DATA_PORT_I(1) when DATA_PORT_OE(1) = '1' else 'Z';
DATA_PORT_OE(1) <= NOT RD;


DATA_PORT_I(2) <= ACK_REG(2);
DATA_PORT(2) <= DATA_PORT_I(2) when DATA_PORT_OE(2) = '1' else 'Z';
DATA_PORT_OE(2) <= NOT RD;


DATA_PORT_I(3) <= ACK_REG(3);
DATA_PORT(3) <= DATA_PORT_I(3) when DATA_PORT_OE(3) = '1' else 'Z';
DATA_PORT_OE(3) <= NOT RD;


DATA_PORT_I(4) <= ACK_REG(4);
DATA_PORT(4) <= DATA_PORT_I(4) when DATA_PORT_OE(4) = '1' else 'Z';
DATA_PORT_OE(4) <= NOT RD;


DATA_PORT_I(5) <= ACK_REG(5);
DATA_PORT(5) <= DATA_PORT_I(5) when DATA_PORT_OE(5) = '1' else 'Z';
DATA_PORT_OE(5) <= NOT RD;


DATA_PORT_I(6) <= ACK_REG(6);
DATA_PORT(6) <= DATA_PORT_I(6) when DATA_PORT_OE(6) = '1' else 'Z';
DATA_PORT_OE(6) <= NOT RD;


DATA_PORT_I(7) <= ACK_REG(7);
DATA_PORT(7) <= DATA_PORT_I(7) when DATA_PORT_OE(7) = '1' else 'Z';
DATA_PORT_OE(7) <= NOT RD;

FTCPE_DATA_REG0: FTCPE port map (DATA_REG(0),DATA_REG_T(0),NOT WR,'0','0');
DATA_REG_T(0) <= ((DATA_PORT(0).PIN AND NOT ADDRESS_REG(0) AND 
	NOT ADDRESS_REG(1) AND NOT ADDRESS_REG(2) AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT DATA_REG(0).LFBK)
	OR (NOT DATA_PORT(0).PIN AND NOT ADDRESS_REG(0) AND 
	NOT ADDRESS_REG(1) AND NOT ADDRESS_REG(2) AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	DATA_REG(0).LFBK));

FTCPE_DATA_REG1: FTCPE port map (DATA_REG(1),DATA_REG_T(1),NOT WR,'0','0');
DATA_REG_T(1) <= ((NOT ADDRESS_REG(0) AND DATA_PORT(1).PIN AND 
	NOT ADDRESS_REG(1) AND NOT ADDRESS_REG(2) AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT DATA_REG(1).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT DATA_PORT(1).PIN AND 
	NOT ADDRESS_REG(1) AND NOT ADDRESS_REG(2) AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	DATA_REG(1).LFBK));

FTCPE_DATA_REG2: FTCPE port map (DATA_REG(2),DATA_REG_T(2),NOT WR,'0','0');
DATA_REG_T(2) <= ((NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(1) AND 
	DATA_PORT(2).PIN AND NOT ADDRESS_REG(2) AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT DATA_REG(2).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(1) AND 
	NOT DATA_PORT(2).PIN AND NOT ADDRESS_REG(2) AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	DATA_REG(2).LFBK));

FTCPE_DATA_REG3: FTCPE port map (DATA_REG(3),DATA_REG_T(3),NOT WR,'0','0');
DATA_REG_T(3) <= ((NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(1) AND NOT ADDRESS_REG(2) AND 
	DATA_PORT(3).PIN AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND NOT ADDRESS_REG(5) AND 
	NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND NOT DATA_REG(3).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(1) AND NOT ADDRESS_REG(2) AND 
	NOT DATA_PORT(3).PIN AND ADDRESS_REG(3) AND NOT ADDRESS_REG(4) AND NOT ADDRESS_REG(5) AND 
	NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND DATA_REG(3).LFBK));

FTCPE_DATA_REG4: FTCPE port map (DATA_REG(4),DATA_REG_T(4),NOT WR,'0','0');
DATA_REG_T(4) <= ((NOT ADDRESS_REG(0) AND DATA_PORT(4).PIN AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT DATA_REG(4).LFBK AND NOT ADDRESS_REG(1).LFBK AND NOT ADDRESS_REG(2).LFBK AND 
	ADDRESS_REG(3).LFBK AND NOT ADDRESS_REG(4).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT DATA_PORT(4).PIN AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	DATA_REG(4).LFBK AND NOT ADDRESS_REG(1).LFBK AND NOT ADDRESS_REG(2).LFBK AND 
	ADDRESS_REG(3).LFBK AND NOT ADDRESS_REG(4).LFBK));

FTCPE_DATA_REG5: FTCPE port map (DATA_REG(5),DATA_REG_T(5),NOT WR,'0','0');
DATA_REG_T(5) <= ((NOT ADDRESS_REG(0) AND DATA_PORT(5).PIN AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT ADDRESS_REG(1).LFBK AND NOT ADDRESS_REG(2).LFBK AND ADDRESS_REG(3).LFBK AND 
	NOT ADDRESS_REG(4).LFBK AND NOT DATA_REG(5).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT DATA_PORT(5).PIN AND 
	NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT ADDRESS_REG(1).LFBK AND NOT ADDRESS_REG(2).LFBK AND ADDRESS_REG(3).LFBK AND 
	NOT ADDRESS_REG(4).LFBK AND DATA_REG(5).LFBK));

FTCPE_DATA_REG6: FTCPE port map (DATA_REG(6),DATA_REG_T(6),NOT WR,'0','0');
DATA_REG_T(6) <= ((NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(5) AND 
	DATA_PORT(6).PIN AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT ADDRESS_REG(1).LFBK AND NOT ADDRESS_REG(2).LFBK AND ADDRESS_REG(3).LFBK AND 
	NOT ADDRESS_REG(4).LFBK AND NOT DATA_REG(6).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(5) AND 
	NOT DATA_PORT(6).PIN AND NOT ADDRESS_REG(6) AND ADDRESS_REG(7) AND 
	NOT ADDRESS_REG(1).LFBK AND NOT ADDRESS_REG(2).LFBK AND ADDRESS_REG(3).LFBK AND 
	NOT ADDRESS_REG(4).LFBK AND DATA_REG(6).LFBK));

FTCPE_DATA_REG7: FTCPE port map (DATA_REG(7),DATA_REG_T(7),NOT WR,'0','0');
DATA_REG_T(7) <= ((NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND 
	DATA_PORT(7).PIN AND ADDRESS_REG(7) AND NOT ADDRESS_REG(1).LFBK AND 
	NOT ADDRESS_REG(2).LFBK AND ADDRESS_REG(3).LFBK AND NOT ADDRESS_REG(4).LFBK AND 
	NOT DATA_REG(7).LFBK)
	OR (NOT ADDRESS_REG(0) AND NOT ADDRESS_REG(5) AND NOT ADDRESS_REG(6) AND 
	NOT DATA_PORT(7).PIN AND ADDRESS_REG(7) AND NOT ADDRESS_REG(1).LFBK AND 
	NOT ADDRESS_REG(2).LFBK AND ADDRESS_REG(3).LFBK AND NOT ADDRESS_REG(4).LFBK AND 
	DATA_REG(7).LFBK));













FTCPE_MUSIC_OUT: FTCPE port map (MUSIC_OUT,'1',MUSIC_OUT_C,'0','0');
MUSIC_OUT_C <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(10).LFBK);

FDCPE_Mtrien_ACK_REG: FDCPE port map (Mtrien_ACK_REG,Mtrien_ACK_REG_D,NOT RD,'0','0');
Mtrien_ACK_REG_D <= (ADDRESS_REG(0) AND NOT ADDRESS_REG(1) AND ADDRESS_REG(2) AND 
	NOT ADDRESS_REG(3) AND ADDRESS_REG(4) AND NOT ADDRESS_REG(5) AND ADDRESS_REG(6) AND 
	NOT ADDRESS_REG(7));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


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 | 12                                                          74 | 
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 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 DATA_PORT<3>                     43 TIE                           
  2 DATA_PORT<2>                     44 TIE                           
  3 DATA_PORT<1>                     45 TIE                           
  4 DATA_PORT<0>                     46 TIE                           
  5 TIE                              47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 CLK                              51 TIE                           
 10 TIE                              52 TIE                           
 11 ALE                              53 TIE                           
 12 TIE                              54 TIE                           
 13 TIE                              55 TIE                           
 14 TIE                              56 TIE                           
 15 TIE                              57 TIE                           
 16 GND                              58 TIE                           
 17 WR                               59 TDO                           
 18 RD                               60 GND                           
 19 MUSIC_OUT                        61 TIE                           
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 TIE                           
 24 TIE                              66 TIE                           
 25 TIE                              67 TIE                           
 26 TIE                              68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 TIE                              73 VCC                           
 32 TIE                              74 TIE                           
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 DATA_PORT<7>                  
 40 TIE                              82 DATA_PORT<6>                  
 41 TIE                              83 DATA_PORT<5>                  
 42 GND                              84 DATA_PORT<4>                  


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25