********** Mapped Logic ********** |
Q(0) <= ((CLK AND CLRB AND D(0))
OR (NOT CLK AND CLRB AND Q_0.LFBK) OR (CLRB AND D(0) AND Q_0.LFBK)); |
Q(1) <= ((CLK AND CLRB AND D(1))
OR (NOT CLK AND CLRB AND Q_1.LFBK) OR (CLRB AND D(1) AND Q_1.LFBK)); |
Q(2) <= ((CLK AND CLRB AND D(2))
OR (NOT CLK AND CLRB AND Q_2.LFBK) OR (CLRB AND D(2) AND Q_2.LFBK)); |
Q(3) <= ((CLK AND CLRB AND D(3))
OR (NOT CLK AND CLRB AND Q_3.LFBK) OR (CLRB AND D(3) AND Q_3.LFBK)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |