Equations

********** Mapped Logic **********
$OpTx$FX_DC$389 <= NOT (COUNT(9)
      XOR
     $OpTx$FX_DC$389 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8)));
$OpTx$FX_DC$391 <= NOT (COUNT(11).LFBK
      XOR
     $OpTx$FX_DC$391 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK));
$OpTx$FX_DC$392 <= NOT (COUNT(12).LFBK
      XOR
     $OpTx$FX_DC$392 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK));
$OpTx$FX_DC$393 <= NOT (COUNT(13).LFBK
      XOR
     $OpTx$FX_DC$393 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK));
$OpTx$FX_DC$396 <= COUNT(14).LFBK
      XOR
     $OpTx$FX_DC$396 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK AND
      COUNT(13).LFBK);
$OpTx$FX_DC$398 <= COUNT(15).LFBK
      XOR
     $OpTx$FX_DC$398 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND
      COUNT(12).LFBK AND COUNT(13).LFBK);
$OpTx$FX_DC$399 <= COUNT(16).LFBK
      XOR
     $OpTx$FX_DC$399 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND
      COUNT(12).LFBK AND COUNT(13).LFBK AND COUNT(15).LFBK);
FTCPE_CLK_16: FTCPE port map (CLK_16,CLK_16_T,CLK,'0','0');
     CLK_16_T <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK);
FTCPE_CNT0: FTCPE port map (CNT(0),'1',CLK,'0','0');
FTCPE_CNT1: FTCPE port map (CNT(1),CNT(0).LFBK,CLK,'0','0');
FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),CLK,'0','0');
     CNT_T(2) <= (CNT(0).LFBK AND CNT(1).LFBK);
FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),CLK,'0','0');
     CNT_T(3) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK);
FTCPE_CNT4: FTCPE port map (CNT(4),CNT_T(4),CLK,'0','0');
     CNT_T(4) <= ((NOT CNT(0))
      OR (NOT CNT(1))
      OR (NOT CNT(2))
      OR (NOT CNT(3))
      OR (NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND
      CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND
      CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND
      CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND
      CNT(19).LFBK));
FTCPE_CNT5: FTCPE port map (CNT(5),CNT_T(5),CLK,'0','0');
     CNT_T(5) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND
      CNT(4).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND
      NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT6: FTCPE port map (CNT(6),CNT_T(6),CLK,'0','0');
     CNT_T(6) <= (CNT(4) AND CNT(5) AND CNT(0).LFBK AND CNT(1).LFBK AND
      CNT(2).LFBK AND CNT(3).LFBK);
FTCPE_CNT7: FTCPE port map (CNT(7),CNT_T(7),CLK,'0','0');
     CNT_T(7) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(4).LFBK AND CNT(5).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT8: FTCPE port map (CNT(8),CNT_T(8),CLK,'0','0');
     CNT_T(8) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT9: FTCPE port map (CNT(9),CNT_T(9),CLK,'0','0');
     CNT_T(9) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK);
FTCPE_CNT10: FTCPE port map (CNT(10),CNT_T(10),CLK,'0','0');
     CNT_T(10) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND
      CNT(9).LFBK);
FTCPE_CNT11: FTCPE port map (CNT(11),CNT_T(11),CLK,'0','0');
     CNT_T(11) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND CNT(9).LFBK);
FTCPE_CNT12: FTCPE port map (CNT(12),CNT_T(12),CLK,'0','0');
     CNT_T(12) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND
      CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT13: FTCPE port map (CNT(13),CNT_T(13),CLK,'0','0');
     CNT_T(13) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(4).LFBK AND
      CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT14: FTCPE port map (CNT(14),CNT_T(14),CLK,'0','0');
     CNT_T(14) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND
      CNT(9).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT15: FTCPE port map (CNT(15),CNT_T(15),CLK,'0','0');
     CNT_T(15) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND CNT(9).LFBK);
FTCPE_CNT16: FTCPE port map (CNT(16),CNT_T(16),CLK,'0','0');
     CNT_T(16) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND CNT(15).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND
      CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT17: FTCPE port map (CNT(17),CNT_T(17),CLK,'0','0');
     CNT_T(17) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND CNT(4).LFBK AND
      CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_CNT18: FTCPE port map (CNT(18),CNT_T(18),CLK,'0','0');
     CNT_T(18) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND
      CNT(9).LFBK);
FTCPE_CNT19: FTCPE port map (CNT(19),CNT_T(19),CLK,'0','0');
     CNT_T(19) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND
      CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      CNT(18).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND CNT(9).LFBK)
      OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND
      NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND
      CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND
      NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND
      CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK));
FTCPE_COUNT0: FTCPE port map (COUNT(0),'1',CLK,'0','0');
FTCPE_COUNT1: FTCPE port map (COUNT(1),COUNT(0).LFBK,CLK,'0','0');
FTCPE_COUNT2: FTCPE port map (COUNT(2),COUNT_T(2),CLK,'0','0');
     COUNT_T(2) <= (COUNT(0).LFBK AND COUNT(1).LFBK);
FTCPE_COUNT3: FTCPE port map (COUNT(3),COUNT_T(3),CLK,'0','0');
     COUNT_T(3) <= (COUNT(0).LFBK AND COUNT(1).LFBK AND COUNT(2).LFBK);
FTCPE_COUNT4: FTCPE port map (COUNT(4),COUNT_T(4),CLK,'0','0');
     COUNT_T(4) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3));
FTCPE_COUNT5: FTCPE port map (COUNT(5),COUNT_T(5),CLK,'0','0');
     COUNT_T(5) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4).LFBK);
FTCPE_COUNT6: FTCPE port map (COUNT(6),COUNT_T(6),CLK,'0','0');
     COUNT_T(6) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4).LFBK AND COUNT(5).LFBK);
FTCPE_COUNT7: FTCPE port map (COUNT(7),COUNT_T(7),CLK,'0','0');
     COUNT_T(7) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4).LFBK AND COUNT(5).LFBK AND COUNT(6).LFBK);
FTCPE_COUNT8: FTCPE port map (COUNT(8),COUNT_T(8),CLK,'0','0');
     COUNT_T(8) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4).LFBK AND COUNT(5).LFBK AND COUNT(6).LFBK AND COUNT(7).LFBK);
FTCPE_COUNT9: FTCPE port map (COUNT(9),COUNT_T(9),CLK,'0','0');
     COUNT_T(9) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4).LFBK AND COUNT(5).LFBK AND COUNT(6).LFBK AND COUNT(7).LFBK AND
      COUNT(8).LFBK);
FTCPE_COUNT10: FTCPE port map (COUNT(10),COUNT_T(10),CLK,'0','0');
     COUNT_T(10) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9));
FTCPE_COUNT11: FTCPE port map (COUNT(11),COUNT_T(11),CLK,'0','0');
     COUNT_T(11) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK);
FTCPE_COUNT12: FTCPE port map (COUNT(12),COUNT(11).EXP,CLK,'0','0');
FTCPE_COUNT13: FTCPE port map (COUNT(13),COUNT_T(13),CLK,'0','0');
     COUNT_T(13) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK);
FTCPE_COUNT14: FTCPE port map (COUNT(14),COUNT_T(14),CLK,'0','0');
     COUNT_T(14) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK AND
      COUNT(13).LFBK);
FTCPE_COUNT15: FTCPE port map (COUNT(15),COUNT_T(15),CLK,'0','0');
     COUNT_T(15) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND
      COUNT(12).LFBK AND COUNT(13).LFBK);
FTCPE_COUNT16: FTCPE port map (COUNT(16),COUNT_T(16),CLK,'0','0');
     COUNT_T(16) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND
      COUNT(12).LFBK AND COUNT(13).LFBK AND COUNT(15).LFBK);
COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND
      COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND
      COUNT(9));
Mcompar_PWM_OUT_cmp_lt0000_ALB29/Mcompar_PWM_OUT_cmp_lt0000_ALB29_D2 <= ((COUNT(9).EXP)
      OR (EXP0_.EXP)
      OR ($OpTx$FX_DC$391 AND PWM_CNT(2).LFBK)
      OR (COUNT(10) AND
      COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK)
      OR (NOT COUNT(10) AND
      NOT COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK)
      OR ($OpTx$FX_DC$389 AND $OpTx$FX_DC$391 AND
      PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK)
      OR ($OpTx$FX_DC$389 AND PWM_CNT(0).LFBK AND
      PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK));
FTCPE_PWM_CNT0: FTCPE port map (PWM_CNT(0),PWM_CNT_T(0),CLK_16,'0','0');
     PWM_CNT_T(0) <= (K1 AND K0);
FTCPE_PWM_CNT1: FTCPE port map (PWM_CNT(1),PWM_CNT_T(1),CLK_16,'0','0');
     PWM_CNT_T(1) <= ((NOT K0 AND PWM_CNT(0).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK));
FTCPE_PWM_CNT2: FTCPE port map (PWM_CNT(2),PWM_CNT_T(2),CLK_16,'0','0');
     PWM_CNT_T(2) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK));
FTCPE_PWM_CNT3: FTCPE port map (PWM_CNT(3),PWM_CNT_T(3),CLK_16,'0','0');
     PWM_CNT_T(3) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND
      PWM_CNT(2).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND
      NOT PWM_CNT(2).LFBK));
FTCPE_PWM_CNT4: FTCPE port map (PWM_CNT(4),PWM_CNT_T(4),CLK_16,'0','0');
     PWM_CNT_T(4) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND
      PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND
      NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK));
FTCPE_PWM_CNT5: FTCPE port map (PWM_CNT(5),PWM_CNT_T(5),CLK_16,'0','0');
     PWM_CNT_T(5) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND
      PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK AND PWM_CNT(4).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND
      NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK AND NOT PWM_CNT(4).LFBK));
FTCPE_PWM_CNT6: FTCPE port map (PWM_CNT(6),PWM_CNT_T(6),CLK_16,'0','0');
     PWM_CNT_T(6) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND
      PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK AND PWM_CNT(4).LFBK AND
      PWM_CNT(5).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND
      NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK AND NOT PWM_CNT(4).LFBK AND
      NOT PWM_CNT(5).LFBK));
FTCPE_PWM_CNT7: FTCPE port map (PWM_CNT(7),PWM_CNT_T(7),CLK_16,'0','0');
     PWM_CNT_T(7) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND
      PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK AND PWM_CNT(4).LFBK AND
      PWM_CNT(5).LFBK AND PWM_CNT(6).LFBK)
      OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND
      NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK AND NOT PWM_CNT(4).LFBK AND
      NOT PWM_CNT(5).LFBK AND NOT PWM_CNT(6).LFBK));
FDCPE_PWM_OUT: FDCPE port map (PWM_OUT,PWM_OUT_D,CLK,'0','0');
     PWM_OUT_D <= ((EXP2_.EXP)
      OR (COUNT(12).EXP)
      OR (PWM_CNT(4) AND NOT SF0/SF0_D2 AND $OpTx$FX_DC$393.LFBK)
      OR (PWM_CNT(6) AND NOT SF0/SF0_D2 AND NOT $OpTx$FX_DC$398.LFBK)
      OR (PWM_CNT(7) AND NOT SF0/SF0_D2 AND NOT $OpTx$FX_DC$399.LFBK)
      OR (PWM_CNT(5) AND NOT COUNT(0) AND NOT SF0/SF0_D2 AND
      NOT COUNT(14).LFBK)
      OR (PWM_CNT(5) AND NOT COUNT(1) AND NOT SF0/SF0_D2 AND
      NOT COUNT(14).LFBK));
SF0/SF0_D2 <= ((PWM_CNT(1).EXP)
      OR ($OpTx$FX_DC$399 AND NOT PWM_CNT(7).LFBK)
      OR ($OpTx$FX_DC$398 AND $OpTx$FX_DC$399 AND
      NOT PWM_CNT(6).LFBK)
      OR ($OpTx$FX_DC$398 AND NOT PWM_CNT(6).LFBK AND
      NOT PWM_CNT(7).LFBK)
      OR ($OpTx$FX_DC$398 AND $OpTx$FX_DC$396 AND
      NOT PWM_CNT(5).LFBK AND NOT PWM_CNT(7).LFBK)
      OR ($OpTx$FX_DC$396 AND NOT PWM_CNT(5).LFBK AND
      NOT PWM_CNT(6).LFBK AND NOT PWM_CNT(7).LFBK));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);