Timing Report

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Design Name CNT4
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Sun May 02 08:11:00 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for QB<2>.Q
Clock to Setup (tCYC) 9.000 ns.
Clock Pad to Output Pad Delay (tCO) 27.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
AUTO_TS_F2F 0.0 9.0 4 4
AUTO_TS_P2P 0.0 27.0 4 4
AUTO_TS_P2F 0.0 2.5 1 1
AUTO_TS_F2P 0.0 3.5 4 4


Constraint: TS1000

Description: PERIOD:PERIOD_QB<2>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_QB<1>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_QB<0>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
QB<0>.Q to Q<0>.D 0.000 9.000 -9.000
QB<1>.Q to Q<1>.D 0.000 9.000 -9.000
QB<2>.Q to Q<2>.D 0.000 9.000 -9.000
QB<3>.Q to Q<3>.D 0.000 9.000 -9.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to Q<3> 0.000 27.000 -27.000
CLK to Q<2> 0.000 20.000 -20.000
CLK to Q<1> 0.000 13.000 -13.000
CLK to Q<0> 0.000 6.000 -6.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to FCLKIO_0 0.000 2.500 -2.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q<0>.Q to Q<0> 0.000 3.500 -3.500
Q<1>.Q to Q<1> 0.000 3.500 -3.500
Q<2>.Q to Q<2> 0.000 3.500 -3.500
Q<3>.Q to Q<3> 0.000 3.500 -3.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
QB<2>.Q 83.333 Limited by Clock Pulse Width for QB<2>.Q
QB<1>.Q 83.333 Limited by Clock Pulse Width for QB<1>.Q
QB<0>.Q 83.333 Limited by Clock Pulse Width for QB<0>.Q
CLK 111.111 Limited by Clock Pulse Width for CLK

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
Q<3> 27.000
Q<2> 20.000
Q<1> 13.000
Q<0> 6.000


Clock to Setup Times for Clocks

Clock to Setup for clock QB<2>.Q
Source Destination Delay
QB<3>.Q Q<3>.D 9.000

Clock to Setup for clock QB<1>.Q
Source Destination Delay
QB<2>.Q Q<2>.D 9.000

Clock to Setup for clock QB<0>.Q
Source Destination Delay
QB<1>.Q Q<1>.D 9.000

Clock to Setup for clock CLK
Source Destination Delay
QB<0>.Q Q<0>.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 13
Number of Timing errors: 13
Analysis Completed: Sun May 02 08:11:00 2010