cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: RS232                               Date:  4-23-2010,  5:43PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
66 /108 ( 61%) 154 /540  ( 29%) 101/216 ( 47%)   66 /108 ( 61%) 12 /69  ( 17%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          16/18       28/36       28          38/90       0/12
FB2          16/18       18/36       18          30/90       0/12
FB3          16/18       23/36       23          32/90       8/12
FB4           2/18        2/36        2           2/90       0/11
FB5           0/18        0/36        0           0/90       0/11
FB6          16/18       30/36       30          52/90       1/11
             -----       -----                   -----       -----     
             66/108     101/216                 154/540      9/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
Global output enable net(s) unused.
The complement of 'RST_B' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :    10      63
Output        :    1           1    |  GCK/IO           :     1       3
Bidirectional :    8           8    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     12          12

** Power Data **

There are 66 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 9 Outputs **

Signal                 Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                   Pts   Inps          No.  Type    Use     Mode Rate State
RX_DATA<7>             2     8     FB3_8   19   I/O     I/O     STD  FAST RESET
RX_DATA<6>             2     8     FB3_9   20   I/O     I/O     STD  FAST RESET
RX_DATA<5>             2     8     FB3_11  21   I/O     I/O     STD  FAST RESET
RX_DATA<4>             2     8     FB3_12  23   I/O     I/O     STD  FAST RESET
RX_DATA<3>             2     8     FB3_14  24   I/O     I/O     STD  FAST RESET
RX_DATA<2>             2     8     FB3_15  25   I/O     I/O     STD  FAST RESET
RX_DATA<1>             2     8     FB3_16  26   I/O     I/O     STD  FAST RESET
RX_DATA<0>             2     8     FB3_17  31   I/O     I/O     STD  FAST RESET
RS232_TX               11    15    FB6_11  52   I/O     O       STD  FAST RESET

** 57 Buried Nodes **

Signal                 Total Total Loc     Pwr  Reg Init
Name                   Pts   Inps          Mode State
clk_bps_rx             1     13    FB1_3   STD  RESET
cnt_rx<9>              2     11    FB1_4   STD  RESET
cnt_rx<5>              2     7     FB1_5   STD  RESET
cnt_rx<4>              2     6     FB1_6   STD  RESET
cnt_rx<3>              2     5     FB1_7   STD  RESET
cnt_rx<1>              2     3     FB1_8   STD  RESET
cnt_rx<12>             2     14    FB1_9   STD  RESET
cnt_rx<10>             2     12    FB1_10  STD  RESET
cnt_rx<0>              2     14    FB1_11  STD  RESET
cnt_tx<2>              3     14    FB1_12  STD  RESET
cnt_tx<11>             3     14    FB1_13  STD  RESET
cnt_rx<8>              3     14    FB1_14  STD  RESET
cnt_rx<7>              3     14    FB1_15  STD  RESET
cnt_rx<6>              3     14    FB1_16  STD  RESET
cnt_rx<2>              3     14    FB1_17  STD  RESET
cnt_rx<11>             3     14    FB1_18  STD  RESET
rs232_rx3              1     1     FB2_3   STD  RESET
rs232_rx2              1     1     FB2_4   STD  RESET
rs232_rx1              1     1     FB2_5   STD  RESET
rs232_rx0              1     1     FB2_6   STD  RESET
clk_bps_tx             1     13    FB2_7   STD  RESET
cnt_tx<9>              2     11    FB2_8   STD  RESET
cnt_tx<5>              2     7     FB2_9   STD  RESET
cnt_tx<4>              2     6     FB2_10  STD  RESET
cnt_tx<3>              2     5     FB2_11  STD  RESET
cnt_tx<1>              2     3     FB2_12  STD  RESET
cnt_tx<12>             2     14    FB2_13  STD  RESET
cnt_tx<10>             2     12    FB2_14  STD  RESET
cnt_tx<0>              2     14    FB2_15  STD  RESET
cnt_tx<8>              3     14    FB2_16  STD  RESET
cnt_tx<7>              3     14    FB2_17  STD  RESET
cnt_tx<6>              3     14    FB2_18  STD  RESET
rx_temp_data<7>        2     8     FB3_3   STD  RESET
rx_temp_data<6>        2     8     FB3_4   STD  RESET
rx_temp_data<5>        2     8     FB3_5   STD  RESET
rx_temp_data<4>        2     8     FB3_6   STD  RESET
rx_temp_data<3>        2     8     FB3_7   STD  RESET
rx_temp_data<2>        2     8     FB3_10  STD  RESET
rx_temp_data<1>        2     8     FB3_13  STD  RESET
rx_temp_data<0>        2     8     FB3_18  STD  RESET

Signal                 Total Total Loc     Pwr  Reg Init
Name                   Pts   Inps          Mode State
rx_int1                1     1     FB4_17  STD  RESET
rx_int0                1     1     FB4_18  STD  RESET
rx_int2                1     1     FB6_3   STD  RESET
num_tx<2>              1     4     FB6_4   STD  RESET
num_rx<1>              1     3     FB6_5   STD  RESET
num_rx<0>              1     2     FB6_6   STD  RESET
num_tx<3>              2     6     FB6_7   STD  RESET
num_tx<1>              2     6     FB6_8   STD  RESET
num_tx<0>              2     6     FB6_9   STD  RESET
num_rx<3>              2     6     FB6_10  STD  RESET
num_rx<2>              2     6     FB6_12  STD  RESET
tx_en                  3     7     FB6_13  STD  RESET
Mtridata_bps_start_tx  3     7     FB6_14  STD  RESET
rx_int                 5     9     FB6_15  STD  RESET
bps_start_tx           5     8     FB6_16  STD  RESET
Mtridata_bps_start_rx  5     9     FB6_17  STD  RESET
bps_start_rx           6     10    FB6_18  STD  RESET

** 3 Inputs **

Signal                 Loc     Pin  Pin     Pin     
Name                           No.  Type    Use     
CLK                    FB1_12  9    GCK/I/O GCK
RST_B                  FB2_5   74   GSR/I/O GSR/I
RS232_RX               FB6_12  53   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               28/8
Number of signals used by logic mapping into function block:  28
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     
clk_bps_rx            1       0     0   4     FB1_3   2     I/O     (b)
cnt_rx<9>             2       0     0   3     FB1_4         (b)     (b)
cnt_rx<5>             2       0     0   3     FB1_5   3     I/O     (b)
cnt_rx<4>             2       0     0   3     FB1_6   4     I/O     (b)
cnt_rx<3>             2       0     0   3     FB1_7         (b)     (b)
cnt_rx<1>             2       0     0   3     FB1_8   5     I/O     (b)
cnt_rx<12>            2       0     0   3     FB1_9   6     I/O     (b)
cnt_rx<10>            2       0     0   3     FB1_10        (b)     (b)
cnt_rx<0>             2       0     0   3     FB1_11  7     I/O     (b)
cnt_tx<2>             3       0     0   2     FB1_12  9     GCK/I/O GCK
cnt_tx<11>            3       0     0   2     FB1_13        (b)     (b)
cnt_rx<8>             3       0     0   2     FB1_14  10    GCK/I/O (b)
cnt_rx<7>             3       0     0   2     FB1_15  11    I/O     (b)
cnt_rx<6>             3       0     0   2     FB1_16  12    GCK/I/O (b)
cnt_rx<2>             3       0     0   2     FB1_17  13    I/O     (b)
cnt_rx<11>            3       0     0   2     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: bps_start_rx      11: cnt_rx<5>.LFBK    20: cnt_tx<1> 
  2: bps_start_tx      12: cnt_rx<6>.LFBK    21: cnt_tx<2>.LFBK 
  3: cnt_rx<0>.LFBK    13: cnt_rx<7>.LFBK    22: cnt_tx<3> 
  4: cnt_rx<10>.LFBK   14: cnt_rx<8>.LFBK    23: cnt_tx<4> 
  5: cnt_rx<11>.LFBK   15: cnt_rx<9>.LFBK    24: cnt_tx<5> 
  6: cnt_rx<12>.LFBK   16: cnt_tx<0>         25: cnt_tx<6> 
  7: cnt_rx<1>.LFBK    17: cnt_tx<10>        26: cnt_tx<7> 
  8: cnt_rx<2>.LFBK    18: cnt_tx<11>.LFBK   27: cnt_tx<8> 
  9: cnt_rx<3>.LFBK    19: cnt_tx<12>        28: cnt_tx<9> 
 10: cnt_rx<4>.LFBK   

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
clk_bps_rx           ..XXXXXXXXXXXXX......................... 13      13
cnt_rx<9>            X.X...XXXXXXXXX......................... 11      11
cnt_rx<5>            X.X...XXXXX............................. 7       7
cnt_rx<4>            X.X...XXXX.............................. 6       6
cnt_rx<3>            X.X...XXX............................... 5       5
cnt_rx<1>            X.X...X................................. 3       3
cnt_rx<12>           X.XXXXXXXXXXXXX......................... 14      14
cnt_rx<10>           X.XX..XXXXXXXXX......................... 12      12
cnt_rx<0>            X.XXXXXXXXXXXXX......................... 14      14
cnt_tx<2>            .X.............XXXXXXXXXXXXX............ 14      14
cnt_tx<11>           .X.............XXXXXXXXXXXXX............ 14      14
cnt_rx<8>            X.XXXXXXXXXXXXX......................... 14      14
cnt_rx<7>            X.XXXXXXXXXXXXX......................... 14      14
cnt_rx<6>            X.XXXXXXXXXXXXX......................... 14      14
cnt_rx<2>            X.XXXXXXXXXXXXX......................... 14      14
cnt_rx<11>           X.XXXXXXXXXXXXX......................... 14      14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   71    I/O     
rs232_rx3             1       0     0   4     FB2_3   72    I/O     (b)
rs232_rx2             1       0     0   4     FB2_4         (b)     (b)
rs232_rx1             1       0     0   4     FB2_5   74    GSR/I/O GSR/I
rs232_rx0             1       0     0   4     FB2_6   75    I/O     (b)
clk_bps_tx            1       0     0   4     FB2_7         (b)     (b)
cnt_tx<9>             2       0     0   3     FB2_8   76    GTS/I/O (b)
cnt_tx<5>             2       0     0   3     FB2_9   77    GTS/I/O (b)
cnt_tx<4>             2       0     0   3     FB2_10        (b)     (b)
cnt_tx<3>             2       0     0   3     FB2_11  79    I/O     (b)
cnt_tx<1>             2       0     0   3     FB2_12  80    I/O     (b)
cnt_tx<12>            2       0     0   3     FB2_13        (b)     (b)
cnt_tx<10>            2       0     0   3     FB2_14  81    I/O     (b)
cnt_tx<0>             2       0     0   3     FB2_15  82    I/O     (b)
cnt_tx<8>             3       0     0   2     FB2_16  83    I/O     (b)
cnt_tx<7>             3       0     0   2     FB2_17  84    I/O     (b)
cnt_tx<6>             3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: RS232_RX           7: cnt_tx<1>.LFBK    13: cnt_tx<7>.LFBK 
  2: bps_start_tx       8: cnt_tx<2>         14: cnt_tx<8>.LFBK 
  3: cnt_tx<0>.LFBK     9: cnt_tx<3>.LFBK    15: cnt_tx<9>.LFBK 
  4: cnt_tx<10>.LFBK   10: cnt_tx<4>.LFBK    16: rs232_rx0.LFBK 
  5: cnt_tx<11>        11: cnt_tx<5>.LFBK    17: rs232_rx1.LFBK 
  6: cnt_tx<12>.LFBK   12: cnt_tx<6>.LFBK    18: rs232_rx2.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
rs232_rx3            .................X...................... 1       1
rs232_rx2            ................X....................... 1       1
rs232_rx1            ...............X........................ 1       1
rs232_rx0            X....................................... 1       1
clk_bps_tx           ..XXXXXXXXXXXXX......................... 13      13
cnt_tx<9>            .XX...XXXXXXXXX......................... 11      11
cnt_tx<5>            .XX...XXXXX............................. 7       7
cnt_tx<4>            .XX...XXXX.............................. 6       6
cnt_tx<3>            .XX...XXX............................... 5       5
cnt_tx<1>            .XX...X................................. 3       3
cnt_tx<12>           .XXXXXXXXXXXXXX......................... 14      14
cnt_tx<10>           .XXX..XXXXXXXXX......................... 12      12
cnt_tx<0>            .XXXXXXXXXXXXXX......................... 14      14
cnt_tx<8>            .XXXXXXXXXXXXXX......................... 14      14
cnt_tx<7>            .XXXXXXXXXXXXXX......................... 14      14
cnt_tx<6>            .XXXXXXXXXXXXXX......................... 14      14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               23/13
Number of signals used by logic mapping into function block:  23
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   14    I/O     
rx_temp_data<7>       2       0     0   3     FB3_3   15    I/O     (b)
rx_temp_data<6>       2       0     0   3     FB3_4         (b)     (b)
rx_temp_data<5>       2       0     0   3     FB3_5   17    I/O     (b)
rx_temp_data<4>       2       0     0   3     FB3_6   18    I/O     (b)
rx_temp_data<3>       2       0     0   3     FB3_7         (b)     (b)
RX_DATA<7>            2       0     0   3     FB3_8   19    I/O     I/O
RX_DATA<6>            2       0     0   3     FB3_9   20    I/O     I/O
rx_temp_data<2>       2       0     0   3     FB3_10        (b)     (b)
RX_DATA<5>            2       0     0   3     FB3_11  21    I/O     I/O
RX_DATA<4>            2       0     0   3     FB3_12  23    I/O     I/O
rx_temp_data<1>       2       0     0   3     FB3_13        (b)     (b)
RX_DATA<3>            2       0     0   3     FB3_14  24    I/O     I/O
RX_DATA<2>            2       0     0   3     FB3_15  25    I/O     I/O
RX_DATA<1>            2       0     0   3     FB3_16  26    I/O     I/O
RX_DATA<0>            2       0     0   3     FB3_17  31    I/O     I/O
rx_temp_data<0>       2       0     0   3     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: RS232_RX             9: rx_data_rx<2>.LFBK    17: rx_temp_data<1>.LFBK 
  2: clk_bps_rx          10: rx_data_rx<3>.LFBK    18: rx_temp_data<2>.LFBK 
  3: num_rx<0>           11: rx_data_rx<4>.LFBK    19: rx_temp_data<3>.LFBK 
  4: num_rx<1>           12: rx_data_rx<5>.LFBK    20: rx_temp_data<4>.LFBK 
  5: num_rx<2>           13: rx_data_rx<6>.LFBK    21: rx_temp_data<5>.LFBK 
  6: num_rx<3>           14: rx_data_rx<7>.LFBK    22: rx_temp_data<6>.LFBK 
  7: rx_data_rx<0>.LFBK  15: rx_int                23: rx_temp_data<7>.LFBK 
  8: rx_data_rx<1>.LFBK  16: rx_temp_data<0>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
rx_temp_data<7>      XXXXXX........X.......X................. 8       8
rx_temp_data<6>      XXXXXX........X......X.................. 8       8
rx_temp_data<5>      XXXXXX........X.....X................... 8       8
rx_temp_data<4>      XXXXXX........X....X.................... 8       8
rx_temp_data<3>      XXXXXX........X...X..................... 8       8
RX_DATA<7>           .XXXXX.......XX.......X................. 8       8
RX_DATA<6>           .XXXXX......X.X......X.................. 8       8
rx_temp_data<2>      XXXXXX........X..X...................... 8       8
RX_DATA<5>           .XXXXX.....X..X.....X................... 8       8
RX_DATA<4>           .XXXXX....X...X....X.................... 8       8
rx_temp_data<1>      XXXXXX........X.X....................... 8       8
RX_DATA<3>           .XXXXX...X....X...X..................... 8       8
RX_DATA<2>           .XXXXX..X.....X..X...................... 8       8
RX_DATA<1>           .XXXXX.X......X.X....................... 8       8
RX_DATA<0>           .XXXXXX.......XX........................ 8       8
rx_temp_data<0>      XXXXXX........XX........................ 8       8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               2/34
Number of signals used by logic mapping into function block:  2
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   57    I/O     
(unused)              0       0     0   5     FB4_3   58    I/O     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   61    I/O     
(unused)              0       0     0   5     FB4_6   62    I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   63    I/O     
(unused)              0       0     0   5     FB4_9   65    I/O     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  66    I/O     
(unused)              0       0     0   5     FB4_12  67    I/O     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  68    I/O     
(unused)              0       0     0   5     FB4_15  69    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
rx_int1               1       0     0   4     FB4_17  70    I/O     (b)
rx_int0               1       0     0   4     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: rx_int             2: rx_int0.LFBK     

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
rx_int1              .X...................................... 1       1
rx_int0              X....................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   32    I/O     
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     
(unused)              0       0     0   5     FB5_9   37    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               30/6
Number of signals used by logic mapping into function block:  30
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB6_1         (b)     (b)
(unused)              0       0     0   5     FB6_2   45    I/O     
rx_int2               1       0     0   4     FB6_3   46    I/O     (b)
num_tx<2>             1       0     0   4     FB6_4         (b)     (b)
num_rx<1>             1       0     0   4     FB6_5   47    I/O     (b)
num_rx<0>             1       0     0   4     FB6_6   48    I/O     (b)
num_tx<3>             2       0     0   3     FB6_7         (b)     (b)
num_tx<1>             2       0     0   3     FB6_8   50    I/O     (b)
num_tx<0>             2       0     0   3     FB6_9   51    I/O     (b)
num_rx<3>             2       0   \/3   0     FB6_10        (b)     (b)
RS232_TX             11       6<-   0   0     FB6_11  52    I/O     O
num_rx<2>             2       0   /\3   0     FB6_12  53    I/O     I
tx_en                 3       0     0   2     FB6_13        (b)     (b)
Mtridata_bps_start_tx
                      3       0     0   2     FB6_14  54    I/O     (b)
rx_int                5       0     0   0     FB6_15  55    I/O     (b)
bps_start_tx          5       0     0   0     FB6_16        (b)     (b)
Mtridata_bps_start_rx
                      5       0     0   0     FB6_17  56    I/O     (b)
bps_start_rx          6       1<-   0   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Mtridata_bps_start_rx.LFBK  11: RX_DATA<7>.PIN    21: num_tx<3>.LFBK 
  2: Mtridata_bps_start_tx.LFBK  12: clk_bps_rx        22: rs232_rx0 
  3: RST_B                       13: clk_bps_tx        23: rs232_rx1 
  4: RX_DATA<0>.PIN              14: num_rx<0>.LFBK    24: rs232_rx2 
  5: RX_DATA<1>.PIN              15: num_rx<1>.LFBK    25: rs232_rx3 
  6: RX_DATA<2>.PIN              16: num_rx<2>.LFBK    26: rs232_tx_r.LFBK 
  7: RX_DATA<3>.PIN              17: num_rx<3>.LFBK    27: rx_int.LFBK 
  8: RX_DATA<4>.PIN              18: num_tx<0>.LFBK    28: rx_int1 
  9: RX_DATA<5>.PIN              19: num_tx<1>.LFBK    29: rx_int2.LFBK 
 10: RX_DATA<6>.PIN              20: num_tx<2>.LFBK    30: tx_en.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
rx_int2              ...........................X............ 1       1
num_tx<2>            ............X....XX..........X.......... 4       4
num_rx<1>            ...........X.X............X............. 3       3
num_rx<0>            ...........X..............X............. 2       2
num_tx<3>            ............X....XXXX........X.......... 6       6
num_tx<1>            ............X....XXXX........X.......... 6       6
num_tx<0>            ............X....XXXX........X.......... 6       6
num_rx<3>            ...........X.XXXX.........X............. 6       6
RS232_TX             ...XXXXXXXX.X....XXXX....X...X.......... 15      15
num_rx<2>            ...........X.XXXX.........X............. 6       6
tx_en                .................XXXX......XXX.......... 7       7
Mtridata_bps_start_tx 
                     .X...............XXXX......XX........... 7       7
rx_int               .............XXXX....XXXX.X............. 9       9
bps_start_tx         .XX..............XXXX......XX........... 8       8
Mtridata_bps_start_rx 
                     X............XXXX....XXXX............... 9       9
bps_start_rx         X.X..........XXXX....XXXX............... 10      10
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********



FDCPE_Mtridata_bps_start_rx: FDCPE port map (Mtridata_bps_start_rx,Mtridata_bps_start_rx_D,CLK,'0','0');
Mtridata_bps_start_rx_D <= ((num_rx(0).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (num_rx(1).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (NOT num_rx(2).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (NOT num_rx(3).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (NOT rs232_rx0 AND NOT rs232_rx1 AND rs232_rx2 AND rs232_rx3));

FTCPE_Mtridata_bps_start_tx: FTCPE port map (Mtridata_bps_start_tx,Mtridata_bps_start_tx_T,CLK,'0','0');
Mtridata_bps_start_tx_T <= ((NOT rx_int1 AND rx_int2.LFBK AND 
	NOT Mtridata_bps_start_tx.LFBK)
	OR (rx_int1 AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND 
	num_tx(0).LFBK AND num_tx(3).LFBK AND Mtridata_bps_start_tx.LFBK)
	OR (NOT num_tx(2).LFBK AND num_tx(1).LFBK AND num_tx(0).LFBK AND 
	num_tx(3).LFBK AND NOT rx_int2.LFBK AND Mtridata_bps_start_tx.LFBK));

FDCPE_RS232_TX: FDCPE port map (RS232_TX,RS232_TX_D,CLK,'0',NOT RST_B);
RS232_TX_D <= ((num_rx(3).EXP)
	OR (num_rx(2).EXP)
	OR (NOT clk_bps_tx AND NOT rs232_tx_r.LFBK)
	OR (NOT rs232_tx_r.LFBK AND NOT tx_en.LFBK)
	OR (clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND 
	NOT num_tx(1).LFBK AND NOT num_tx(0).LFBK AND NOT num_tx(3).LFBK)
	OR (clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND 
	NOT num_tx(1).LFBK AND NOT num_tx(0).LFBK AND NOT RX_DATA(7).PIN)
	OR (clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND 
	NOT num_tx(0).LFBK AND NOT num_tx(3).LFBK AND NOT RX_DATA(1).PIN));

FTCPE_RX_DATA0: FTCPE port map (RX_DATA(0),RX_DATA_T(0),CLK,NOT RST_B,'0');
RX_DATA_T(0) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(0).LFBK AND 
	NOT rx_temp_data(0).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(0).LFBK AND 
	rx_temp_data(0).LFBK));

FTCPE_RX_DATA1: FTCPE port map (RX_DATA(1),RX_DATA_T(1),CLK,NOT RST_B,'0');
RX_DATA_T(1) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(1).LFBK AND 
	NOT rx_temp_data(1).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(1).LFBK AND 
	rx_temp_data(1).LFBK));

FTCPE_RX_DATA2: FTCPE port map (RX_DATA(2),RX_DATA_T(2),CLK,NOT RST_B,'0');
RX_DATA_T(2) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(2).LFBK AND 
	NOT rx_temp_data(2).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(2).LFBK AND 
	rx_temp_data(2).LFBK));

FTCPE_RX_DATA3: FTCPE port map (RX_DATA(3),RX_DATA_T(3),CLK,NOT RST_B,'0');
RX_DATA_T(3) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(3).LFBK AND 
	NOT rx_temp_data(3).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(3).LFBK AND 
	rx_temp_data(3).LFBK));

FTCPE_RX_DATA4: FTCPE port map (RX_DATA(4),RX_DATA_T(4),CLK,NOT RST_B,'0');
RX_DATA_T(4) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(4).LFBK AND 
	NOT rx_temp_data(4).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(4).LFBK AND 
	rx_temp_data(4).LFBK));

FTCPE_RX_DATA5: FTCPE port map (RX_DATA(5),RX_DATA_T(5),CLK,NOT RST_B,'0');
RX_DATA_T(5) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(5).LFBK AND 
	NOT rx_temp_data(5).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(5).LFBK AND 
	rx_temp_data(5).LFBK));

FTCPE_RX_DATA6: FTCPE port map (RX_DATA(6),RX_DATA_T(6),CLK,NOT RST_B,'0');
RX_DATA_T(6) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(6).LFBK AND 
	NOT rx_temp_data(6).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(6).LFBK AND 
	rx_temp_data(6).LFBK));

FTCPE_RX_DATA7: FTCPE port map (RX_DATA(7),RX_DATA_T(7),CLK,NOT RST_B,'0');
RX_DATA_T(7) <= ((rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND rx_data_rx(7).LFBK AND 
	NOT rx_temp_data(7).LFBK)
	OR (rx_int AND NOT clk_bps_rx AND NOT num_rx(0) AND NOT num_rx(1) AND 
	num_rx(2) AND num_rx(3) AND NOT rx_data_rx(7).LFBK AND 
	rx_temp_data(7).LFBK));

FDCPE_bps_start_rx: FDCPE port map (bps_start_rx,bps_start_rx_D,CLK,'0','0');
bps_start_rx_D <= ((EXP0_.EXP)
	OR (num_rx(0).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (num_rx(1).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (NOT num_rx(2).LFBK AND Mtridata_bps_start_rx.LFBK)
	OR (NOT num_rx(3).LFBK AND Mtridata_bps_start_rx.LFBK));

FDCPE_bps_start_tx: FDCPE port map (bps_start_tx,bps_start_tx_D,CLK,'0','0');
bps_start_tx_D <= ((rx_int1 AND NOT Mtridata_bps_start_tx.LFBK)
	OR (NOT rx_int2.LFBK AND NOT Mtridata_bps_start_tx.LFBK)
	OR (rx_int1 AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND 
	num_tx(0).LFBK AND num_tx(3).LFBK)
	OR (NOT num_tx(2).LFBK AND num_tx(1).LFBK AND num_tx(0).LFBK AND 
	num_tx(3).LFBK AND NOT rx_int2.LFBK));

FDCPE_clk_bps_rx: FDCPE port map (clk_bps_rx,clk_bps_rx_D,CLK,NOT RST_B,'0');
clk_bps_rx_D <= (NOT cnt_rx(0).LFBK AND cnt_rx(10).LFBK AND 
	NOT cnt_rx(11).LFBK AND cnt_rx(1).LFBK AND NOT cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	NOT cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK);

FDCPE_clk_bps_tx: FDCPE port map (clk_bps_tx,clk_bps_tx_D,CLK,NOT RST_B,'0');
clk_bps_tx_D <= (NOT cnt_tx(11) AND NOT cnt_tx(2) AND NOT cnt_tx(0).LFBK AND 
	cnt_tx(10).LFBK AND cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND 
	cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND NOT cnt_tx(8).LFBK AND 
	NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK);

FTCPE_cnt_rx0: FTCPE port map (cnt_rx(0),cnt_rx_T(0),CLK,NOT RST_B,'0');
cnt_rx_T(0) <= ((NOT bps_start_rx AND NOT cnt_rx(0).LFBK)
	OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));

FDCPE_cnt_rx1: FDCPE port map (cnt_rx(1),cnt_rx_D(1),CLK,NOT RST_B,'0');
cnt_rx_D(1) <= ((bps_start_rx AND cnt_rx(0).LFBK AND NOT cnt_rx(1).LFBK)
	OR (bps_start_rx AND NOT cnt_rx(0).LFBK AND cnt_rx(1).LFBK));

FTCPE_cnt_rx2: FTCPE port map (cnt_rx(2),cnt_rx_T(2),CLK,NOT RST_B,'0');
cnt_rx_T(2) <= ((NOT bps_start_rx AND cnt_rx(2).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK)
	OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));

FTCPE_cnt_rx3: FTCPE port map (cnt_rx(3),cnt_rx_T(3),CLK,NOT RST_B,'0');
cnt_rx_T(3) <= ((NOT bps_start_rx AND cnt_rx(3).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK));

FTCPE_cnt_rx4: FTCPE port map (cnt_rx(4),cnt_rx_T(4),CLK,NOT RST_B,'0');
cnt_rx_T(4) <= ((NOT bps_start_rx AND cnt_rx(4).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK));

FTCPE_cnt_rx5: FTCPE port map (cnt_rx(5),cnt_rx_T(5),CLK,NOT RST_B,'0');
cnt_rx_T(5) <= ((NOT bps_start_rx AND cnt_rx(5).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK));

FTCPE_cnt_rx6: FTCPE port map (cnt_rx(6),cnt_rx_T(6),CLK,NOT RST_B,'0');
cnt_rx_T(6) <= ((NOT bps_start_rx AND cnt_rx(6).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK)
	OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));

FTCPE_cnt_rx7: FTCPE port map (cnt_rx(7),cnt_rx_T(7),CLK,NOT RST_B,'0');
cnt_rx_T(7) <= ((NOT bps_start_rx AND cnt_rx(7).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND 
	cnt_rx(6).LFBK)
	OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));

FTCPE_cnt_rx8: FTCPE port map (cnt_rx(8),cnt_rx_T(8),CLK,NOT RST_B,'0');
cnt_rx_T(8) <= ((NOT bps_start_rx AND cnt_rx(8).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND 
	cnt_rx(6).LFBK AND cnt_rx(7).LFBK)
	OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));

FTCPE_cnt_rx9: FTCPE port map (cnt_rx(9),cnt_rx_T(9),CLK,NOT RST_B,'0');
cnt_rx_T(9) <= ((NOT bps_start_rx AND cnt_rx(9).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND 
	cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND cnt_rx(8).LFBK));

FTCPE_cnt_rx10: FTCPE port map (cnt_rx(10),cnt_rx_T(10),CLK,NOT RST_B,'0');
cnt_rx_T(10) <= ((NOT bps_start_rx AND cnt_rx(10).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(1).LFBK AND 
	cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND 
	cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND cnt_rx(8).LFBK AND cnt_rx(9).LFBK));

FTCPE_cnt_rx11: FTCPE port map (cnt_rx(11),cnt_rx_T(11),CLK,NOT RST_B,'0');
cnt_rx_T(11) <= ((NOT bps_start_rx AND cnt_rx(11).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(10).LFBK AND 
	cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND cnt_rx(4).LFBK AND 
	cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND cnt_rx(8).LFBK AND 
	cnt_rx(9).LFBK)
	OR (NOT cnt_rx(0).LFBK AND NOT cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND NOT cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND NOT cnt_rx(3).LFBK AND 
	NOT cnt_rx(4).LFBK AND NOT cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND NOT cnt_rx(9).LFBK AND NOT cnt_rx(12).LFBK));

FTCPE_cnt_rx12: FTCPE port map (cnt_rx(12),cnt_rx_T(12),CLK,NOT RST_B,'0');
cnt_rx_T(12) <= ((NOT bps_start_rx AND cnt_rx(12).LFBK)
	OR (bps_start_rx AND cnt_rx(0).LFBK AND cnt_rx(10).LFBK AND 
	cnt_rx(11).LFBK AND cnt_rx(1).LFBK AND cnt_rx(2).LFBK AND cnt_rx(3).LFBK AND 
	cnt_rx(4).LFBK AND cnt_rx(5).LFBK AND cnt_rx(6).LFBK AND cnt_rx(7).LFBK AND 
	cnt_rx(8).LFBK AND cnt_rx(9).LFBK));

FTCPE_cnt_tx0: FTCPE port map (cnt_tx(0),cnt_tx_T(0),CLK,NOT RST_B,'0');
cnt_tx_T(0) <= ((NOT bps_start_tx AND NOT cnt_tx(0).LFBK)
	OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND 
	NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND 
	NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND 
	NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));

FDCPE_cnt_tx1: FDCPE port map (cnt_tx(1),cnt_tx_D(1),CLK,NOT RST_B,'0');
cnt_tx_D(1) <= ((bps_start_tx AND cnt_tx(0).LFBK AND NOT cnt_tx(1).LFBK)
	OR (bps_start_tx AND NOT cnt_tx(0).LFBK AND cnt_tx(1).LFBK));

FTCPE_cnt_tx2: FTCPE port map (cnt_tx(2),cnt_tx_T(2),CLK,NOT RST_B,'0');
cnt_tx_T(2) <= ((NOT bps_start_tx AND cnt_tx(2).LFBK)
	OR (cnt_tx(0) AND cnt_tx(1) AND bps_start_tx)
	OR (NOT cnt_tx(0) AND NOT cnt_tx(10) AND NOT cnt_tx(1) AND NOT cnt_tx(3) AND 
	NOT cnt_tx(4) AND NOT cnt_tx(5) AND cnt_tx(6) AND cnt_tx(7) AND cnt_tx(8) AND 
	NOT cnt_tx(9) AND NOT cnt_tx(12) AND cnt_tx(11).LFBK AND cnt_tx(2).LFBK));

FTCPE_cnt_tx3: FTCPE port map (cnt_tx(3),cnt_tx_T(3),CLK,NOT RST_B,'0');
cnt_tx_T(3) <= ((NOT bps_start_tx AND cnt_tx(3).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK));

FTCPE_cnt_tx4: FTCPE port map (cnt_tx(4),cnt_tx_T(4),CLK,NOT RST_B,'0');
cnt_tx_T(4) <= ((NOT bps_start_tx AND cnt_tx(4).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK));

FTCPE_cnt_tx5: FTCPE port map (cnt_tx(5),cnt_tx_T(5),CLK,NOT RST_B,'0');
cnt_tx_T(5) <= ((NOT bps_start_tx AND cnt_tx(5).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK));

FTCPE_cnt_tx6: FTCPE port map (cnt_tx(6),cnt_tx_T(6),CLK,NOT RST_B,'0');
cnt_tx_T(6) <= ((NOT bps_start_tx AND cnt_tx(6).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK)
	OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND 
	NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND 
	NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND 
	NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));

FTCPE_cnt_tx7: FTCPE port map (cnt_tx(7),cnt_tx_T(7),CLK,NOT RST_B,'0');
cnt_tx_T(7) <= ((NOT bps_start_tx AND cnt_tx(7).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND 
	cnt_tx(6).LFBK)
	OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND 
	NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND 
	NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND 
	NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));

FTCPE_cnt_tx8: FTCPE port map (cnt_tx(8),cnt_tx_T(8),CLK,NOT RST_B,'0');
cnt_tx_T(8) <= ((NOT bps_start_tx AND cnt_tx(8).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND 
	cnt_tx(6).LFBK AND cnt_tx(7).LFBK)
	OR (cnt_tx(11) AND cnt_tx(2) AND NOT cnt_tx(0).LFBK AND 
	NOT cnt_tx(10).LFBK AND NOT cnt_tx(1).LFBK AND NOT cnt_tx(3).LFBK AND NOT cnt_tx(4).LFBK AND 
	NOT cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND 
	NOT cnt_tx(9).LFBK AND NOT cnt_tx(12).LFBK));

FTCPE_cnt_tx9: FTCPE port map (cnt_tx(9),cnt_tx_T(9),CLK,NOT RST_B,'0');
cnt_tx_T(9) <= ((NOT bps_start_tx AND cnt_tx(9).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND 
	cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK));

FTCPE_cnt_tx10: FTCPE port map (cnt_tx(10),cnt_tx_T(10),CLK,NOT RST_B,'0');
cnt_tx_T(10) <= ((NOT bps_start_tx AND cnt_tx(10).LFBK)
	OR (cnt_tx(2) AND bps_start_tx AND cnt_tx(0).LFBK AND 
	cnt_tx(1).LFBK AND cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND 
	cnt_tx(6).LFBK AND cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND cnt_tx(9).LFBK));

FTCPE_cnt_tx11: FTCPE port map (cnt_tx(11),cnt_tx_T(11),CLK,NOT RST_B,'0');
cnt_tx_T(11) <= ((NOT bps_start_tx AND cnt_tx(11).LFBK)
	OR (cnt_tx(0) AND cnt_tx(10) AND cnt_tx(1) AND cnt_tx(3) AND 
	cnt_tx(4) AND cnt_tx(5) AND cnt_tx(6) AND cnt_tx(7) AND cnt_tx(8) AND 
	cnt_tx(9) AND bps_start_tx AND cnt_tx(2).LFBK)
	OR (NOT cnt_tx(0) AND NOT cnt_tx(10) AND NOT cnt_tx(1) AND NOT cnt_tx(3) AND 
	NOT cnt_tx(4) AND NOT cnt_tx(5) AND cnt_tx(6) AND cnt_tx(7) AND cnt_tx(8) AND 
	NOT cnt_tx(9) AND NOT cnt_tx(12) AND cnt_tx(11).LFBK AND cnt_tx(2).LFBK));

FTCPE_cnt_tx12: FTCPE port map (cnt_tx(12),cnt_tx_T(12),CLK,NOT RST_B,'0');
cnt_tx_T(12) <= ((NOT bps_start_tx AND cnt_tx(12).LFBK)
	OR (cnt_tx(11) AND cnt_tx(2) AND bps_start_tx AND 
	cnt_tx(0).LFBK AND cnt_tx(10).LFBK AND cnt_tx(1).LFBK AND 
	cnt_tx(3).LFBK AND cnt_tx(4).LFBK AND cnt_tx(5).LFBK AND cnt_tx(6).LFBK AND 
	cnt_tx(7).LFBK AND cnt_tx(8).LFBK AND cnt_tx(9).LFBK));

FTCPE_num_rx0: FTCPE port map (num_rx(0),num_rx_T(0),CLK,NOT RST_B,'0');
num_rx_T(0) <= (clk_bps_rx AND rx_int.LFBK);

FTCPE_num_rx1: FTCPE port map (num_rx(1),num_rx_T(1),CLK,NOT RST_B,'0');
num_rx_T(1) <= (clk_bps_rx AND rx_int.LFBK AND num_rx(0).LFBK);

FTCPE_num_rx2: FTCPE port map (num_rx(2),num_rx_T(2),CLK,NOT RST_B,'0');
num_rx_T(2) <= ((clk_bps_rx AND rx_int.LFBK AND num_rx(0).LFBK AND 
	num_rx(1).LFBK)
	OR (NOT clk_bps_rx AND rx_int.LFBK AND NOT num_rx(0).LFBK AND 
	NOT num_rx(1).LFBK AND num_rx(2).LFBK AND num_rx(3).LFBK));

FTCPE_num_rx3: FTCPE port map (num_rx(3),num_rx_T(3),CLK,NOT RST_B,'0');
num_rx_T(3) <= ((clk_bps_rx AND rx_int.LFBK AND num_rx(0).LFBK AND 
	num_rx(1).LFBK AND num_rx(2).LFBK)
	OR (NOT clk_bps_rx AND rx_int.LFBK AND NOT num_rx(0).LFBK AND 
	NOT num_rx(1).LFBK AND num_rx(2).LFBK AND num_rx(3).LFBK));

FTCPE_num_tx0: FTCPE port map (num_tx(0),num_tx_T(0),CLK,NOT RST_B,'0');
num_tx_T(0) <= ((clk_bps_tx AND tx_en.LFBK)
	OR (tx_en.LFBK AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND 
	num_tx(0).LFBK AND num_tx(3).LFBK));

FTCPE_num_tx1: FTCPE port map (num_tx(1),num_tx_T(1),CLK,NOT RST_B,'0');
num_tx_T(1) <= ((clk_bps_tx AND tx_en.LFBK AND num_tx(0).LFBK)
	OR (tx_en.LFBK AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND 
	num_tx(0).LFBK AND num_tx(3).LFBK));

FTCPE_num_tx2: FTCPE port map (num_tx(2),num_tx_T(2),CLK,NOT RST_B,'0');
num_tx_T(2) <= (clk_bps_tx AND tx_en.LFBK AND num_tx(1).LFBK AND 
	num_tx(0).LFBK);

FTCPE_num_tx3: FTCPE port map (num_tx(3),num_tx_T(3),CLK,NOT RST_B,'0');
num_tx_T(3) <= ((clk_bps_tx AND tx_en.LFBK AND num_tx(2).LFBK AND 
	num_tx(1).LFBK AND num_tx(0).LFBK)
	OR (NOT clk_bps_tx AND tx_en.LFBK AND NOT num_tx(2).LFBK AND 
	num_tx(1).LFBK AND num_tx(0).LFBK AND num_tx(3).LFBK));

FDCPE_rs232_rx0: FDCPE port map (rs232_rx0,RS232_RX,CLK,NOT RST_B,'0');

FDCPE_rs232_rx1: FDCPE port map (rs232_rx1,rs232_rx0.LFBK,CLK,NOT RST_B,'0');

FDCPE_rs232_rx2: FDCPE port map (rs232_rx2,rs232_rx1.LFBK,CLK,NOT RST_B,'0');

FDCPE_rs232_rx3: FDCPE port map (rs232_rx3,rs232_rx2.LFBK,CLK,NOT RST_B,'0');

FDCPE_rx_int: FDCPE port map (rx_int,rx_int_D,CLK,NOT RST_B,'0');
rx_int_D <= ((rx_int.LFBK AND num_rx(0).LFBK)
	OR (rx_int.LFBK AND num_rx(1).LFBK)
	OR (rx_int.LFBK AND NOT num_rx(2).LFBK)
	OR (rx_int.LFBK AND NOT num_rx(3).LFBK)
	OR (NOT rs232_rx0 AND NOT rs232_rx1 AND rs232_rx2 AND rs232_rx3));

FDCPE_rx_int0: FDCPE port map (rx_int0,rx_int,CLK,NOT RST_B,'0');

FDCPE_rx_int1: FDCPE port map (rx_int1,rx_int0.LFBK,CLK,NOT RST_B,'0');

FDCPE_rx_int2: FDCPE port map (rx_int2,rx_int1,CLK,NOT RST_B,'0');

FTCPE_rx_temp_data0: FTCPE port map (rx_temp_data(0),rx_temp_data_T(0),CLK,NOT RST_B,'0');
rx_temp_data_T(0) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	NOT num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(0).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	NOT num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND rx_temp_data(0).LFBK));

FTCPE_rx_temp_data1: FTCPE port map (rx_temp_data(1),rx_temp_data_T(1),CLK,NOT RST_B,'0');
rx_temp_data_T(1) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(1).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND rx_temp_data(1).LFBK));

FTCPE_rx_temp_data2: FTCPE port map (rx_temp_data(2),rx_temp_data_T(2),CLK,NOT RST_B,'0');
rx_temp_data_T(2) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(2).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	num_rx(1) AND NOT num_rx(2) AND NOT num_rx(3) AND rx_temp_data(2).LFBK));

FTCPE_rx_temp_data3: FTCPE port map (rx_temp_data(3),rx_temp_data_T(3),CLK,NOT RST_B,'0');
rx_temp_data_T(3) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(3).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(3).LFBK));

FTCPE_rx_temp_data4: FTCPE port map (rx_temp_data(4),rx_temp_data_T(4),CLK,NOT RST_B,'0');
rx_temp_data_T(4) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(4).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	NOT num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(4).LFBK));

FTCPE_rx_temp_data5: FTCPE port map (rx_temp_data(5),rx_temp_data_T(5),CLK,NOT RST_B,'0');
rx_temp_data_T(5) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(5).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(5).LFBK));

FTCPE_rx_temp_data6: FTCPE port map (rx_temp_data(6),rx_temp_data_T(6),CLK,NOT RST_B,'0');
rx_temp_data_T(6) <= ((RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND NOT rx_temp_data(6).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND num_rx(0) AND 
	num_rx(1) AND num_rx(2) AND NOT num_rx(3) AND rx_temp_data(6).LFBK));

FTCPE_rx_temp_data7: FTCPE port map (rx_temp_data(7),rx_temp_data_T(7),CLK,NOT RST_B,'0');
rx_temp_data_T(7) <= ((RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	NOT num_rx(1) AND NOT num_rx(2) AND num_rx(3) AND NOT rx_temp_data(7).LFBK)
	OR (NOT RS232_RX AND rx_int AND clk_bps_rx AND NOT num_rx(0) AND 
	NOT num_rx(1) AND NOT num_rx(2) AND num_rx(3) AND rx_temp_data(7).LFBK));

FTCPE_tx_en: FTCPE port map (tx_en,tx_en_T,CLK,NOT RST_B,'0');
tx_en_T <= ((NOT rx_int1 AND NOT tx_en.LFBK AND rx_int2.LFBK)
	OR (rx_int1 AND tx_en.LFBK AND NOT num_tx(2).LFBK AND 
	num_tx(1).LFBK AND num_tx(0).LFBK AND num_tx(3).LFBK)
	OR (tx_en.LFBK AND NOT num_tx(2).LFBK AND num_tx(1).LFBK AND 
	num_tx(0).LFBK AND num_tx(3).LFBK AND NOT rx_int2.LFBK));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              43 TIE                           
  2 TIE                              44 TIE                           
  3 TIE                              45 TIE                           
  4 TIE                              46 TIE                           
  5 TIE                              47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 CLK                              51 TIE                           
 10 TIE                              52 RS232_TX                      
 11 TIE                              53 RS232_RX                      
 12 TIE                              54 TIE                           
 13 TIE                              55 TIE                           
 14 TIE                              56 TIE                           
 15 TIE                              57 TIE                           
 16 GND                              58 TIE                           
 17 TIE                              59 TDO                           
 18 TIE                              60 GND                           
 19 RX_DATA<7>                       61 TIE                           
 20 RX_DATA<6>                       62 TIE                           
 21 RX_DATA<5>                       63 TIE                           
 22 VCC                              64 VCC                           
 23 RX_DATA<4>                       65 TIE                           
 24 RX_DATA<3>                       66 TIE                           
 25 RX_DATA<2>                       67 TIE                           
 26 RX_DATA<1>                       68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 RX_DATA<0>                       73 VCC                           
 32 TIE                              74 RST_B                         
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 TIE                           
 40 TIE                              82 TIE                           
 41 TIE                              83 TIE                           
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25