********** Mapped Logic ********** |
FTCPE_COUNTER0: FTCPE port map (COUNTER(0),'1',CLK,'0','0'); |
FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER(0).LFBK,CLK,'0','0'); |
FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
COUNTER_T(2) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK); |
FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
COUNTER_T(3) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2)); |
FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
COUNTER_T(4) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK); |
FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
COUNTER_T(5) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK AND COUNTER(4).LFBK); |
FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
COUNTER_T(6) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK); |
FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
COUNTER_T(7) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK); |
FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
COUNTER_T(8) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK); |
FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
COUNTER_T(9) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK); |
FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
COUNTER_T(10) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK); |
FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
COUNTER_T(11) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(10).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK); |
FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
COUNTER_T(12) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK); |
FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
COUNTER_T(13) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK); |
FDCPE_SEG0: FDCPE port map (SEG(0),SEG_D(0),CLK,'0','0');
SEG_D(0) <= ((NOT STATUS(1).LFBK AND STATUS(0).LFBK AND NOT STATUS(2).LFBK) OR (NOT STATUS(1).LFBK AND NOT STATUS(0).LFBK AND STATUS(2).LFBK)); |
FDCPE_SEG1: FDCPE port map (SEG(1),SEG_D(1),CLK,'0','0');
SEG_D(1) <= ((STATUS(1).LFBK AND NOT STATUS(0).LFBK AND STATUS(2).LFBK) OR (NOT STATUS(1).LFBK AND STATUS(0).LFBK AND STATUS(2).LFBK)); |
FDCPE_SEG2: FDCPE port map (SEG(2),SEG_D(2),CLK,'0','0');
SEG_D(2) <= (NOT STATUS(2) AND STATUS(1) AND NOT STATUS(0)); |
FDCPE_SEG3: FDCPE port map (SEG(3),SEG_D(3),CLK,'0','0');
SEG_D(3) <= ((STATUS(2) AND STATUS(1) AND STATUS(0)) OR (STATUS(2) AND NOT STATUS(1) AND NOT STATUS(0)) OR (NOT STATUS(2) AND NOT STATUS(1) AND STATUS(0))); |
FDCPE_SEG4: FDCPE port map (SEG(4),SEG_D(4),CLK,'0','0');
SEG_D(4) <= ((NOT STATUS(2) AND NOT STATUS(0)) OR (STATUS(1) AND NOT STATUS(0))); |
FDCPE_SEG5: FDCPE port map (SEG(5),SEG_D(5),CLK,'0','0');
SEG_D(5) <= ((STATUS(2) AND NOT STATUS(1)) OR (STATUS(2) AND NOT STATUS(0)) OR (NOT STATUS(1) AND NOT STATUS(0))); |
FDCPE_SEG6: FDCPE port map (SEG(6),SEG_D(6),CLK,'0','0');
SEG_D(6) <= ((NOT STATUS(2) AND NOT STATUS(1)) OR (STATUS(2) AND STATUS(1) AND STATUS(0))); |
SEG(7) <= '0'; |
FDCPE_SEL0: FDCPE port map (SEL(0),SEL_D(0),CLK,'0','0');
SEL_D(0) <= (NOT STATUS(2) AND NOT STATUS(1) AND NOT STATUS(0)); |
FDCPE_SEL1: FDCPE port map (SEL(1),SEL_D(1),CLK,'0','0');
SEL_D(1) <= (NOT STATUS(2) AND NOT STATUS(1) AND STATUS(0)); |
FDCPE_SEL2: FDCPE port map (SEL(2),SEL_D(2),CLK,'0','0');
SEL_D(2) <= (NOT STATUS(2) AND STATUS(1) AND NOT STATUS(0)); |
FDCPE_SEL3: FDCPE port map (SEL(3),SEL_D(3),CLK,'0','0');
SEL_D(3) <= (NOT STATUS(2) AND STATUS(1) AND STATUS(0)); |
FDCPE_SEL4: FDCPE port map (SEL(4),SEL_D(4),CLK,'0','0');
SEL_D(4) <= (STATUS(2) AND NOT STATUS(1) AND NOT STATUS(0)); |
FDCPE_SEL5: FDCPE port map (SEL(5),SEL_D(5),CLK,'0','0');
SEL_D(5) <= (STATUS(2) AND NOT STATUS(1) AND STATUS(0)); |
FDCPE_SEL6: FDCPE port map (SEL(6),SEL_D(6),CLK,'0','0');
SEL_D(6) <= (STATUS(2) AND STATUS(1) AND NOT STATUS(0)); |
FDCPE_SEL7: FDCPE port map (SEL(7),SEL_D(7),CLK,'0','0');
SEL_D(7) <= (STATUS(2) AND STATUS(1) AND STATUS(0)); |
FTCPE_STATUS0: FTCPE port map (STATUS(0),STATUS_T(0),CLK,'0','0');
STATUS_T(0) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(13).LFBK); |
FTCPE_STATUS1: FTCPE port map (STATUS(1),STATUS_T(1),CLK,'0','0');
STATUS_T(1) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND STATUS(0).LFBK AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(13).LFBK); |
FTCPE_STATUS2: FTCPE port map (STATUS(2),STATUS_T(2),CLK,'0','0');
STATUS_T(2) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND STATUS(1).LFBK AND STATUS(0).LFBK AND COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(13).LFBK); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |