cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: SONG                                Date:  4-22-2010,  8:09PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
65 /108 ( 60%) 219 /540  ( 41%) 97 /216 ( 45%)   65 /108 ( 60%) 2  /69  (  3%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          16/18       24/36       24          31/90       0/12
FB2          16/18       24/36       24          52/90       0/12
FB3          16/18       30/36       30          72/90       1/12
FB4          16/18       18/36       18          63/90       0/11
FB5           1/18        1/36        1           1/90       0/11
FB6           0/18        0/36        0           0/90       0/11
             -----       -----                   -----       -----     
             65/108      97/216                 219/540      1/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :     1      63
Output        :    1           1    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      2           2

** Power Data **

There are 65 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 1 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
BZ_OUT              1     15    FB3_8   19   I/O     O       STD  FAST RESET

** 64 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
CNT<23>             1     23    FB1_3   STD  RESET
CNT<22>             1     22    FB1_4   STD  RESET
CNT<20>             1     20    FB1_5   STD  RESET
CNT<17>             1     17    FB1_6   STD  RESET
CNT<13>             1     13    FB1_7   STD  RESET
CLK_4               1     24    FB1_8   STD  RESET
CNT<9>              2     24    FB1_9   STD  RESET
CNT<7>              2     24    FB1_10  STD  RESET
CNT<21>             2     24    FB1_11  STD  RESET
CNT<19>             2     24    FB1_12  STD  RESET
CNT<18>             2     24    FB1_13  STD  RESET
CNT<16>             2     24    FB1_14  STD  RESET
CNT<15>             2     24    FB1_15  STD  RESET
CNT<14>             2     24    FB1_16  STD  RESET
CNT<10>             2     24    FB1_17  STD  RESET
CNT<6>              7     24    FB1_18  STD  RESET
COUNTER_BEGIN<14>   7     6     FB2_1   STD  RESET
CNT<8>              1     8     FB2_3   STD  RESET
CNT<5>              1     5     FB2_4   STD  RESET
CNT<4>              1     4     FB2_5   STD  RESET
CNT<3>              1     3     FB2_6   STD  RESET
CNT<2>              1     2     FB2_7   STD  RESET
CNT<1>              1     1     FB2_8   STD  RESET
CNT<12>             1     12    FB2_9   STD  RESET
CNT<11>             1     11    FB2_10  STD  RESET
CNT<0>              0     0     FB2_11  STD  RESET
COUNTER_BEGIN<8>    6     6     FB2_12  STD  RESET
COUNTER_BEGIN<7>    6     6     FB2_13  STD  RESET
COUNTER_BEGIN<6>    6     6     FB2_14  STD  RESET
COUNTER_BEGIN<3>    6     6     FB2_16  STD  RESET
COUNTER_BEGIN<11>   6     6     FB2_17  STD  RESET
COUNTER_BEGIN<4>    7     6     FB2_18  STD  RESET
COUNTER<7>          8     16    FB3_1   STD  RESET
COUNTER<0>          1     16    FB3_3   STD  RESET
COUNTER<1>          2     16    FB3_4   STD  RESET
COUNTER<14>         2     16    FB3_5   STD  RESET
COUNTER<2>          3     16    FB3_6   STD  RESET
COUNTER<13>         3     16    FB3_7   STD  RESET
COUNTER<3>          4     16    FB3_9   STD  RESET
COUNTER<12>         4     16    FB3_10  STD  RESET

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
COUNTER<4>          5     16    FB3_11  STD  RESET
COUNTER<11>         5     16    FB3_12  STD  RESET
COUNTER<5>          6     16    FB3_13  STD  RESET
COUNTER<10>         6     16    FB3_14  STD  RESET
COUNTER<9>          7     16    FB3_15  STD  RESET
COUNTER<6>          7     16    FB3_17  STD  RESET
COUNTER<8>          8     16    FB3_18  STD  RESET
LOOP_CNT<4>         2     5     FB4_3   STD  RESET
LOOP_CNT<3>         2     4     FB4_4   STD  RESET
LOOP_CNT<2>         2     3     FB4_5   STD  RESET
LOOP_CNT<1>         2     2     FB4_6   STD  RESET
L<0>                2     5     FB4_7   STD  RESET
M<2>                4     6     FB4_8   STD  RESET
COUNTER_BEGIN<5>    4     6     FB4_9   STD  RESET
COUNTER_BEGIN<10>   4     6     FB4_10  STD  RESET
M<0>                5     6     FB4_11  STD  RESET
COUNTER_BEGIN<9>    5     6     FB4_12  STD  RESET
COUNTER_BEGIN<2>    5     6     FB4_13  STD  RESET
COUNTER_BEGIN<1>    5     6     FB4_14  STD  RESET
COUNTER_BEGIN<13>   5     6     FB4_15  STD  RESET
COUNTER_BEGIN<12>   5     6     FB4_16  STD  RESET
COUNTER_BEGIN<0>    5     6     FB4_17  STD  RESET
M<1>                6     6     FB4_18  STD  RESET
LOOP_CNT<0>         1     1     FB5_18  STD  RESET

** 1 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
CLK                 FB1_12  9    GCK/I/O GCK

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               24/12
Number of signals used by logic mapping into function block:  24
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     
CNT<23>               1       0     0   4     FB1_3   2     I/O     (b)
CNT<22>               1       0     0   4     FB1_4         (b)     (b)
CNT<20>               1       0     0   4     FB1_5   3     I/O     (b)
CNT<17>               1       0     0   4     FB1_6   4     I/O     (b)
CNT<13>               1       0     0   4     FB1_7         (b)     (b)
CLK_4                 1       0     0   4     FB1_8   5     I/O     (b)
CNT<9>                2       0     0   3     FB1_9   6     I/O     (b)
CNT<7>                2       0     0   3     FB1_10        (b)     (b)
CNT<21>               2       0     0   3     FB1_11  7     I/O     (b)
CNT<19>               2       0     0   3     FB1_12  9     GCK/I/O GCK
CNT<18>               2       0     0   3     FB1_13        (b)     (b)
CNT<16>               2       0     0   3     FB1_14  10    GCK/I/O (b)
CNT<15>               2       0     0   3     FB1_15  11    I/O     (b)
CNT<14>               2       0     0   3     FB1_16  12    GCK/I/O (b)
CNT<10>               2       0   \/2   1     FB1_17  13    I/O     (b)
CNT<6>                7       2<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CNT<0>             9: CNT<17>.LFBK      17: CNT<2> 
  2: CNT<10>.LFBK      10: CNT<18>.LFBK      18: CNT<3> 
  3: CNT<11>           11: CNT<19>.LFBK      19: CNT<4> 
  4: CNT<12>           12: CNT<1>            20: CNT<5> 
  5: CNT<13>.LFBK      13: CNT<20>.LFBK      21: CNT<6>.LFBK 
  6: CNT<14>.LFBK      14: CNT<21>.LFBK      22: CNT<7>.LFBK 
  7: CNT<15>.LFBK      15: CNT<22>.LFBK      23: CNT<8> 
  8: CNT<16>.LFBK      16: CNT<23>.LFBK      24: CNT<9>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
CNT<23>              XXXXXXXXXXXXXXX.XXXXXXXX................ 23      23
CNT<22>              XXXXXXXXXXXXXX..XXXXXXXX................ 22      22
CNT<20>              XXXXXXXXXXXX....XXXXXXXX................ 20      20
CNT<17>              XXXXXXXX...X....XXXXXXXX................ 17      17
CNT<13>              XXXX.......X....XXXXXXXX................ 13      13
CLK_4                XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<9>               XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<7>               XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<21>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<19>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<18>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<16>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<15>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<14>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<10>              XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
CNT<6>               XXXXXXXXXXXXXXXXXXXXXXXX................ 24      24
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               24/12
Number of signals used by logic mapping into function block:  24
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
COUNTER_BEGIN<14>     7       4<- /\2   0     FB2_1         (b)     (b)
(unused)              0       0   /\4   1     FB2_2   71    I/O     (b)
CNT<8>                1       0     0   4     FB2_3   72    I/O     (b)
CNT<5>                1       0     0   4     FB2_4         (b)     (b)
CNT<4>                1       0     0   4     FB2_5   74    GSR/I/O (b)
CNT<3>                1       0     0   4     FB2_6   75    I/O     (b)
CNT<2>                1       0     0   4     FB2_7         (b)     (b)
CNT<1>                1       0     0   4     FB2_8   76    GTS/I/O (b)
CNT<12>               1       0     0   4     FB2_9   77    GTS/I/O (b)
CNT<11>               1       0     0   4     FB2_10        (b)     (b)
CNT<0>                0       0   \/3   2     FB2_11  79    I/O     (b)
COUNTER_BEGIN<8>      6       3<- \/2   0     FB2_12  80    I/O     (b)
COUNTER_BEGIN<7>      6       2<- \/1   0     FB2_13        (b)     (b)
COUNTER_BEGIN<6>      6       1<-   0   0     FB2_14  81    I/O     (b)
(unused)              0       0   \/2   3     FB2_15  82    I/O     (b)
COUNTER_BEGIN<3>      6       2<- \/1   0     FB2_16  83    I/O     (b)
COUNTER_BEGIN<11>     6       1<-   0   0     FB2_17  84    I/O     (b)
COUNTER_BEGIN<4>      7       2<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK_4              9: CNT<5>.LFBK             17: COUNTER_BEGIN<4>.LFBK 
  2: CNT<0>.LFBK       10: CNT<6>                  18: COUNTER_BEGIN<6>.LFBK 
  3: CNT<10>           11: CNT<7>                  19: COUNTER_BEGIN<7>.LFBK 
  4: CNT<11>.LFBK      12: CNT<8>.LFBK             20: COUNTER_BEGIN<8>.LFBK 
  5: CNT<1>.LFBK       13: CNT<9>                  21: L<0> 
  6: CNT<2>.LFBK       14: COUNTER_BEGIN<11>.LFBK  22: M<0> 
  7: CNT<3>.LFBK       15: COUNTER_BEGIN<14>.LFBK  23: M<1> 
  8: CNT<4>.LFBK       16: COUNTER_BEGIN<3>.LFBK   24: M<2> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
COUNTER_BEGIN<14>    X.............X.....XXXX................ 6       6
CNT<8>               .X..XXXXXXX............................. 8       8
CNT<5>               .X..XXXX................................ 5       5
CNT<4>               .X..XXX................................. 4       4
CNT<3>               .X..XX.................................. 3       3
CNT<2>               .X..X................................... 2       2
CNT<1>               .X...................................... 1       1
CNT<12>              .XXXXXXXXXXXX........................... 12      12
CNT<11>              .XX.XXXXXXXXX........................... 11      11
CNT<0>               ........................................ 0       0
COUNTER_BEGIN<8>     X..................XXXXX................ 6       6
COUNTER_BEGIN<7>     X.................X.XXXX................ 6       6
COUNTER_BEGIN<6>     X................X..XXXX................ 6       6
COUNTER_BEGIN<3>     X..............X....XXXX................ 6       6
COUNTER_BEGIN<11>    X............X......XXXX................ 6       6
COUNTER_BEGIN<4>     X...............X...XXXX................ 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               30/6
Number of signals used by logic mapping into function block:  30
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
COUNTER<7>            8       3<-   0   0     FB3_1         (b)     (b)
(unused)              0       0   /\3   2     FB3_2   14    I/O     (b)
COUNTER<0>            1       0     0   4     FB3_3   15    I/O     (b)
COUNTER<1>            2       0     0   3     FB3_4         (b)     (b)
COUNTER<14>           2       0     0   3     FB3_5   17    I/O     (b)
COUNTER<2>            3       0     0   2     FB3_6   18    I/O     (b)
COUNTER<13>           3       0     0   2     FB3_7         (b)     (b)
BZ_OUT                1       0   \/2   2     FB3_8   19    I/O     O
COUNTER<3>            4       2<- \/3   0     FB3_9   20    I/O     (b)
COUNTER<12>           4       3<- \/4   0     FB3_10        (b)     (b)
COUNTER<4>            5       4<- \/4   0     FB3_11  21    I/O     (b)
COUNTER<11>           5       4<- \/4   0     FB3_12  23    I/O     (b)
COUNTER<5>            6       4<- \/3   0     FB3_13        (b)     (b)
COUNTER<10>           6       3<- \/2   0     FB3_14  24    I/O     (b)
COUNTER<9>            7       2<-   0   0     FB3_15  25    I/O     (b)
(unused)              0       0   \/5   0     FB3_16  26    I/O     (b)
COUNTER<6>            7       5<- \/3   0     FB3_17  31    I/O     (b)
COUNTER<8>            8       3<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: COUNTER<0>.LFBK   11: COUNTER<5>.LFBK    21: COUNTER_BEGIN<14> 
  2: COUNTER<10>.LFBK  12: COUNTER<6>.LFBK    22: COUNTER_BEGIN<1> 
  3: COUNTER<11>.LFBK  13: COUNTER<7>.LFBK    23: COUNTER_BEGIN<2> 
  4: COUNTER<12>.LFBK  14: COUNTER<8>.LFBK    24: COUNTER_BEGIN<3> 
  5: COUNTER<13>.LFBK  15: COUNTER<9>.LFBK    25: COUNTER_BEGIN<4> 
  6: COUNTER<14>.LFBK  16: COUNTER_BEGIN<0>   26: COUNTER_BEGIN<5> 
  7: COUNTER<1>.LFBK   17: COUNTER_BEGIN<10>  27: COUNTER_BEGIN<6> 
  8: COUNTER<2>.LFBK   18: COUNTER_BEGIN<11>  28: COUNTER_BEGIN<7> 
  9: COUNTER<3>.LFBK   19: COUNTER_BEGIN<12>  29: COUNTER_BEGIN<8> 
 10: COUNTER<4>.LFBK   20: COUNTER_BEGIN<13>  30: COUNTER_BEGIN<9> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
COUNTER<7>           XXXXXXXXXXXXXXX............X............ 16      16
COUNTER<0>           XXXXXXXXXXXXXXXX........................ 16      16
COUNTER<1>           XXXXXXXXXXXXXXX......X.................. 16      16
COUNTER<14>          XXXXXXXXXXXXXXX.....X................... 16      16
COUNTER<2>           XXXXXXXXXXXXXXX.......X................. 16      16
COUNTER<13>          XXXXXXXXXXXXXXX....X.................... 16      16
BZ_OUT               XXXXXXXXXXXXXXX......................... 15      15
COUNTER<3>           XXXXXXXXXXXXXXX........X................ 16      16
COUNTER<12>          XXXXXXXXXXXXXXX...X..................... 16      16
COUNTER<4>           XXXXXXXXXXXXXXX.........X............... 16      16
COUNTER<11>          XXXXXXXXXXXXXXX..X...................... 16      16
COUNTER<5>           XXXXXXXXXXXXXXX..........X.............. 16      16
COUNTER<10>          XXXXXXXXXXXXXXX.X....................... 16      16
COUNTER<9>           XXXXXXXXXXXXXXX..............X.......... 16      16
COUNTER<6>           XXXXXXXXXXXXXXX...........X............. 16      16
COUNTER<8>           XXXXXXXXXXXXXXX.............X........... 16      16
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB4_1         (b)     (b)
(unused)              0       0     0   5     FB4_2   57    I/O     
LOOP_CNT<4>           2       0     0   3     FB4_3   58    I/O     (b)
LOOP_CNT<3>           2       0     0   3     FB4_4         (b)     (b)
LOOP_CNT<2>           2       0     0   3     FB4_5   61    I/O     (b)
LOOP_CNT<1>           2       0     0   3     FB4_6   62    I/O     (b)
L<0>                  2       0     0   3     FB4_7         (b)     (b)
M<2>                  4       0     0   1     FB4_8   63    I/O     (b)
COUNTER_BEGIN<5>      4       0     0   1     FB4_9   65    I/O     (b)
COUNTER_BEGIN<10>     4       0     0   1     FB4_10        (b)     (b)
M<0>                  5       0     0   0     FB4_11  66    I/O     (b)
COUNTER_BEGIN<9>      5       0     0   0     FB4_12  67    I/O     (b)
COUNTER_BEGIN<2>      5       0     0   0     FB4_13        (b)     (b)
COUNTER_BEGIN<1>      5       0     0   0     FB4_14  68    I/O     (b)
COUNTER_BEGIN<13>     5       0     0   0     FB4_15  69    I/O     (b)
COUNTER_BEGIN<12>     5       0     0   0     FB4_16        (b)     (b)
COUNTER_BEGIN<0>      5       0     0   0     FB4_17  70    I/O     (b)
M<1>                  6       1<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK_4                    7: COUNTER_BEGIN<2>.LFBK  13: LOOP_CNT<2>.LFBK 
  2: COUNTER_BEGIN<0>.LFBK    8: COUNTER_BEGIN<5>.LFBK  14: LOOP_CNT<3>.LFBK 
  3: COUNTER_BEGIN<10>.LFBK   9: COUNTER_BEGIN<9>.LFBK  15: LOOP_CNT<4>.LFBK 
  4: COUNTER_BEGIN<12>.LFBK  10: L<0>.LFBK              16: M<0>.LFBK 
  5: COUNTER_BEGIN<13>.LFBK  11: LOOP_CNT<0>            17: M<1>.LFBK 
  6: COUNTER_BEGIN<1>.LFBK   12: LOOP_CNT<1>.LFBK       18: M<2>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LOOP_CNT<4>          X.........XXXX.......................... 5       5
LOOP_CNT<3>          X.........XXX........................... 4       4
LOOP_CNT<2>          X.........XX............................ 3       3
LOOP_CNT<1>          X.........X............................. 2       2
L<0>                 X..........XXXX......................... 5       5
M<2>                 X.........XXXXX......................... 6       6
COUNTER_BEGIN<5>     X......X.X.....XXX...................... 6       6
COUNTER_BEGIN<10>    X.X......X.....XXX...................... 6       6
M<0>                 X.........XXXXX......................... 6       6
COUNTER_BEGIN<9>     X.......XX.....XXX...................... 6       6
COUNTER_BEGIN<2>     X.....X..X.....XXX...................... 6       6
COUNTER_BEGIN<1>     X....X...X.....XXX...................... 6       6
COUNTER_BEGIN<13>    X...X....X.....XXX...................... 6       6
COUNTER_BEGIN<12>    X..X.....X.....XXX...................... 6       6
COUNTER_BEGIN<0>     XX.......X.....XXX...................... 6       6
M<1>                 X.........XXXXX......................... 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               1/35
Number of signals used by logic mapping into function block:  1
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   32    I/O     
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     
(unused)              0       0     0   5     FB5_9   37    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
LOOP_CNT<0>           1       0     0   4     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK_4            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
LOOP_CNT<0>          X....................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
(unused)              0       0     0   5     FB6_2   45    I/O     
(unused)              0       0     0   5     FB6_3   46    I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   47    I/O     
(unused)              0       0     0   5     FB6_6   48    I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   50    I/O     
(unused)              0       0     0   5     FB6_9   51    I/O     
(unused)              0       0     0   5     FB6_10        (b)     
(unused)              0       0     0   5     FB6_11  52    I/O     
(unused)              0       0     0   5     FB6_12  53    I/O     
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  54    I/O     
(unused)              0       0     0   5     FB6_15  55    I/O     
(unused)              0       0     0   5     FB6_16        (b)     
(unused)              0       0     0   5     FB6_17  56    I/O     
(unused)              0       0     0   5     FB6_18        (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********

FTCPE_BZ_OUT: FTCPE port map (BZ_OUT,'1',BZ_OUT_C,'0','0');
BZ_OUT_C <= (COUNTER(0).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND 
	COUNTER(14).LFBK);

FTCPE_CLK_4: FTCPE port map (CLK_4,CLK_4_T,CLK,'0','0');
CLK_4_T <= (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK);

FTCPE_CNT0: FTCPE port map (CNT(0),'1',CLK,'0','0');

FTCPE_CNT1: FTCPE port map (CNT(1),CNT(0).LFBK,CLK,'0','0');

FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),CLK,'0','0');
CNT_T(2) <= (CNT(0).LFBK AND CNT(1).LFBK);

FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),CLK,'0','0');
CNT_T(3) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK);

FTCPE_CNT4: FTCPE port map (CNT(4),CNT_T(4),CLK,'0','0');
CNT_T(4) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND 
	CNT(3).LFBK);

FTCPE_CNT5: FTCPE port map (CNT(5),CNT_T(5),CLK,'0','0');
CNT_T(5) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND 
	CNT(3).LFBK AND CNT(4).LFBK);

FTCPE_CNT6: FTCPE port map (CNT(6),CNT_T(6),CLK,'0','0');
CNT_T(6) <= ((NOT CNT(0))
	OR (NOT CNT(1))
	OR (NOT CNT(2))
	OR (NOT CNT(3))
	OR (NOT CNT(4))
	OR (CNT(10).EXP));

FTCPE_CNT7: FTCPE port map (CNT(7),CNT_T(7),CLK,'0','0');
CNT_T(7) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND 
	CNT(5) AND CNT(6).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND CNT(7).LFBK AND CNT(9).LFBK AND 
	NOT CNT(23).LFBK));

FTCPE_CNT8: FTCPE port map (CNT(8),CNT_T(8),CLK,'0','0');
CNT_T(8) <= (CNT(6) AND CNT(7) AND CNT(0).LFBK AND CNT(1).LFBK AND 
	CNT(2).LFBK AND CNT(3).LFBK AND CNT(4).LFBK AND CNT(5).LFBK);

FTCPE_CNT9: FTCPE port map (CNT(9),CNT_T(9),CLK,'0','0');
CNT_T(9) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND 
	CNT(5) AND CNT(8) AND CNT(6).LFBK AND CNT(7).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT10: FTCPE port map (CNT(10),CNT_T(10),CLK,'0','0');
CNT_T(10) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4) AND 
	CNT(5) AND CNT(8) AND CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT11: FTCPE port map (CNT(11),CNT_T(11),CLK,'0','0');
CNT_T(11) <= (CNT(10) AND CNT(6) AND CNT(7) AND CNT(9) AND 
	CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK AND 
	CNT(4).LFBK AND CNT(5).LFBK AND CNT(8).LFBK);

FTCPE_CNT12: FTCPE port map (CNT(12),CNT_T(12),CLK,'0','0');
CNT_T(12) <= (CNT(10) AND CNT(6) AND CNT(7) AND CNT(9) AND 
	CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK AND 
	CNT(4).LFBK AND CNT(5).LFBK AND CNT(8).LFBK AND CNT(11).LFBK);

FTCPE_CNT13: FTCPE port map (CNT(13),CNT_T(13),CLK,'0','0');
CNT_T(13) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK);

FTCPE_CNT14: FTCPE port map (CNT(14),CNT_T(14),CLK,'0','0');
CNT_T(14) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT15: FTCPE port map (CNT(15),CNT_T(15),CLK,'0','0');
CNT_T(15) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT16: FTCPE port map (CNT(16),CNT_T(16),CLK,'0','0');
CNT_T(16) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(6).LFBK AND 
	CNT(7).LFBK AND CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT17: FTCPE port map (CNT(17),CNT_T(17),CLK,'0','0');
CNT_T(17) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK);

FTCPE_CNT18: FTCPE port map (CNT(18),CNT_T(18),CLK,'0','0');
CNT_T(18) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(17).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT19: FTCPE port map (CNT(19),CNT_T(19),CLK,'0','0');
CNT_T(19) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(17).LFBK AND CNT(18).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT20: FTCPE port map (CNT(20),CNT_T(20),CLK,'0','0');
CNT_T(20) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(6).LFBK AND 
	CNT(7).LFBK AND CNT(9).LFBK);

FTCPE_CNT21: FTCPE port map (CNT(21),CNT_T(21),CLK,'0','0');
CNT_T(21) <= ((CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(20).LFBK AND 
	CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK)
	OR (CNT(0) AND NOT CNT(11) AND NOT CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND NOT CNT(8) AND CNT(10).LFBK AND 
	NOT CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	NOT CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND NOT CNT(20).LFBK AND 
	CNT(21).LFBK AND NOT CNT(22).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK AND NOT CNT(23).LFBK));

FTCPE_CNT22: FTCPE port map (CNT(22),CNT_T(22),CLK,'0','0');
CNT_T(22) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(20).LFBK AND 
	CNT(21).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND CNT(9).LFBK);

FTCPE_CNT23: FTCPE port map (CNT(23),CNT_T(23),CLK,'0','0');
CNT_T(23) <= (CNT(0) AND CNT(11) AND CNT(12) AND CNT(1) AND CNT(2) AND 
	CNT(3) AND CNT(4) AND CNT(5) AND CNT(8) AND CNT(10).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND 
	CNT(17).LFBK AND CNT(18).LFBK AND CNT(19).LFBK AND CNT(20).LFBK AND 
	CNT(21).LFBK AND CNT(22).LFBK AND CNT(6).LFBK AND CNT(7).LFBK AND 
	CNT(9).LFBK);

FTCPE_COUNTER0: FTCPE port map (COUNTER(0),COUNTER_T(0),CLK,'0','0');
COUNTER_T(0) <= (COUNTER_BEGIN(0) AND COUNTER(0).LFBK AND 
	COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(1).LFBK AND COUNTER(2).LFBK AND 
	COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND 
	COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK AND COUNTER(14).LFBK);

FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER_T(1),CLK,'0','0');
COUNTER_T(1) <= ((NOT COUNTER(0).LFBK)
	OR (COUNTER_BEGIN(1) AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND 
	COUNTER(14).LFBK));

FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
COUNTER_T(2) <= ((NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK)
	OR (COUNTER_BEGIN(2) AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(14).LFBK));

FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
COUNTER_T(3) <= ((BZ_OUT_OBUF.EXP)
	OR (NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK));

FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
COUNTER_T(4) <= ((COUNTER(12).EXP)
	OR (NOT COUNTER(0).LFBK));

FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
COUNTER_T(5) <= ((COUNTER(11).EXP)
	OR (NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK));

FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
COUNTER_T(6) <= ((EXP3_.EXP)
	OR (NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK));

FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
COUNTER_T(7) <= ((EXP2_.EXP)
	OR (NOT COUNTER(0).LFBK)
	OR (NOT COUNTER(1).LFBK)
	OR (NOT COUNTER(2).LFBK)
	OR (NOT COUNTER(3).LFBK)
	OR (NOT COUNTER(4).LFBK));

FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
COUNTER_T(8) <= ((COUNTER(6).EXP)
	OR (COUNTER(0).LFBK AND NOT COUNTER(10).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(11).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(12).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(13).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	NOT COUNTER(8).LFBK));

FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
COUNTER_T(9) <= ((COUNTER(10).EXP)
	OR (COUNTER(0).LFBK AND NOT COUNTER(10).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(11).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(12).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(13).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND NOT COUNTER(9).LFBK));

FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
COUNTER_T(10) <= ((COUNTER(5).EXP)
	OR (COUNTER(0).LFBK AND NOT COUNTER(10).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(11).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND NOT COUNTER(12).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK));

FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
COUNTER_T(11) <= ((COUNTER(4).EXP)
	OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND 
	NOT COUNTER(11).LFBK AND COUNTER(1).LFBK AND COUNTER(2).LFBK AND 
	COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND 
	COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK));

FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
COUNTER_T(12) <= ((COUNTER(3).EXP)
	OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND NOT COUNTER(12).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK));

FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
COUNTER_T(13) <= ((NOT COUNTER_BEGIN(13) AND COUNTER(0).LFBK AND 
	COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND COUNTER(12).LFBK AND NOT COUNTER(13).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND NOT COUNTER(14).LFBK));

FTCPE_COUNTER14: FTCPE port map (COUNTER(14),COUNTER_T(14),CLK,'0','0');
COUNTER_T(14) <= ((NOT COUNTER_BEGIN(14) AND COUNTER(0).LFBK AND 
	COUNTER(10).LFBK AND COUNTER(11).LFBK AND COUNTER(12).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(1).LFBK AND COUNTER(2).LFBK AND 
	COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND 
	COUNTER(6).LFBK AND COUNTER(7).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK)
	OR (COUNTER(0).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(11).LFBK AND COUNTER(12).LFBK AND COUNTER(13).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND 
	NOT COUNTER(14).LFBK));

FTCPE_COUNTER_BEGIN0: FTCPE port map (COUNTER_BEGIN(0),COUNTER_BEGIN_T(0),CLK_4,'0','0');
COUNTER_BEGIN_T(0) <= ((M(2).LFBK AND NOT L(0).LFBK AND NOT COUNTER_BEGIN(0).LFBK AND 
	NOT M(1).LFBK)
	OR (NOT M(2).LFBK AND NOT L(0).LFBK AND M(0).LFBK AND 
	COUNTER_BEGIN(0).LFBK)
	OR (NOT M(2).LFBK AND NOT L(0).LFBK AND NOT M(0).LFBK AND 
	NOT COUNTER_BEGIN(0).LFBK)
	OR (NOT M(2).LFBK AND NOT M(0).LFBK AND NOT COUNTER_BEGIN(0).LFBK AND 
	NOT M(1).LFBK));

FTCPE_COUNTER_BEGIN1: FTCPE port map (COUNTER_BEGIN(1),COUNTER_BEGIN_T(1),CLK_4,'0','0');
COUNTER_BEGIN_T(1) <= ((NOT M(2).LFBK AND NOT L(0).LFBK AND M(1).LFBK AND 
	NOT COUNTER_BEGIN(1).LFBK)
	OR (NOT M(2).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND 
	NOT COUNTER_BEGIN(1).LFBK)
	OR (NOT L(0).LFBK AND M(0).LFBK AND NOT M(1).LFBK AND 
	COUNTER_BEGIN(1).LFBK)
	OR (NOT L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND 
	NOT COUNTER_BEGIN(1).LFBK));

FDCPE_COUNTER_BEGIN2: FDCPE port map (COUNTER_BEGIN(2),COUNTER_BEGIN_D(2),CLK_4,'0','0');
COUNTER_BEGIN_D(2) <= ((L(0).LFBK AND NOT COUNTER_BEGIN(2).LFBK)
	OR (M(2).LFBK AND M(1).LFBK AND NOT COUNTER_BEGIN(2).LFBK)
	OR (M(2).LFBK AND NOT L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK)
	OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK));

FDCPE_COUNTER_BEGIN3: FDCPE port map (COUNTER_BEGIN(3),COUNTER_BEGIN_D(3),CLK_4,'0','0');
COUNTER_BEGIN_D(3) <= ((EXP1_.EXP)
	OR (M(2) AND NOT COUNTER_BEGIN(3).LFBK)
	OR (M(1) AND L(0) AND NOT COUNTER_BEGIN(3).LFBK)
	OR (NOT M(1) AND M(2) AND NOT L(0)));

FDCPE_COUNTER_BEGIN4: FDCPE port map (COUNTER_BEGIN(4),COUNTER_BEGIN_D(4),CLK_4,'0','0');
COUNTER_BEGIN_D(4) <= ((COUNTER_BEGIN(14).EXP)
	OR (M(1) AND M(2) AND COUNTER_BEGIN(4).LFBK)
	OR (M(1) AND L(0) AND COUNTER_BEGIN(4).LFBK)
	OR (M(2) AND L(0) AND COUNTER_BEGIN(4).LFBK)
	OR (L(0) AND M(0) AND COUNTER_BEGIN(4).LFBK));

FTCPE_COUNTER_BEGIN5: FTCPE port map (COUNTER_BEGIN(5),COUNTER_BEGIN_T(5),CLK_4,'0','0');
COUNTER_BEGIN_T(5) <= ((NOT M(2).LFBK AND NOT L(0).LFBK AND NOT COUNTER_BEGIN(5).LFBK)
	OR (NOT L(0).LFBK AND NOT M(1).LFBK AND NOT COUNTER_BEGIN(5).LFBK)
	OR (NOT M(2).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND 
	NOT COUNTER_BEGIN(5).LFBK));

FTCPE_COUNTER_BEGIN6: FTCPE port map (COUNTER_BEGIN(6),COUNTER_BEGIN_T(6),CLK_4,'0','0');
COUNTER_BEGIN_T(6) <= ((COUNTER_BEGIN(7).EXP)
	OR (NOT M(1) AND NOT M(2) AND NOT M(0) AND NOT COUNTER_BEGIN(6).LFBK)
	OR (NOT M(1) AND NOT L(0) AND NOT M(0) AND NOT COUNTER_BEGIN(6).LFBK)
	OR (NOT M(2) AND NOT L(0) AND M(0) AND NOT COUNTER_BEGIN(6).LFBK)
	OR (NOT M(1) AND M(2) AND NOT L(0) AND M(0) AND 
	COUNTER_BEGIN(6).LFBK));

FDCPE_COUNTER_BEGIN7: FDCPE port map (COUNTER_BEGIN(7),COUNTER_BEGIN_D(7),CLK_4,'0','0');
COUNTER_BEGIN_D(7) <= ((COUNTER_BEGIN(8).EXP)
	OR (L(0) AND NOT COUNTER_BEGIN(7).LFBK)
	OR (M(1) AND M(2) AND NOT COUNTER_BEGIN(7).LFBK)
	OR (NOT M(1) AND NOT L(0) AND M(0)));

FDCPE_COUNTER_BEGIN8: FDCPE port map (COUNTER_BEGIN(8),COUNTER_BEGIN_D(8),CLK_4,'0','0');
COUNTER_BEGIN_D(8) <= ((CNT(0).EXP)
	OR (M(1) AND M(2) AND COUNTER_BEGIN(8).LFBK)
	OR (M(1) AND L(0) AND COUNTER_BEGIN(8).LFBK));

FTCPE_COUNTER_BEGIN9: FTCPE port map (COUNTER_BEGIN(9),COUNTER_BEGIN_T(9),CLK_4,'0','0');
COUNTER_BEGIN_T(9) <= ((M(2).LFBK AND NOT L(0).LFBK AND NOT M(1).LFBK AND 
	COUNTER_BEGIN(9).LFBK)
	OR (NOT M(2).LFBK AND NOT L(0).LFBK AND M(1).LFBK AND 
	COUNTER_BEGIN(9).LFBK)
	OR (NOT M(2).LFBK AND NOT L(0).LFBK AND NOT M(1).LFBK AND 
	NOT COUNTER_BEGIN(9).LFBK)
	OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND 
	COUNTER_BEGIN(9).LFBK));

FTCPE_COUNTER_BEGIN10: FTCPE port map (COUNTER_BEGIN(10),COUNTER_BEGIN_T(10),CLK_4,'0','0');
COUNTER_BEGIN_T(10) <= ((NOT L(0).LFBK AND NOT M(1).LFBK AND NOT COUNTER_BEGIN(10).LFBK)
	OR (NOT M(2).LFBK AND NOT L(0).LFBK AND M(1).LFBK AND 
	COUNTER_BEGIN(10).LFBK)
	OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK AND 
	COUNTER_BEGIN(10).LFBK));

FDCPE_COUNTER_BEGIN11: FDCPE port map (COUNTER_BEGIN(11),COUNTER_BEGIN_D(11),CLK_4,'0','0');
COUNTER_BEGIN_D(11) <= ((COUNTER_BEGIN(3).EXP)
	OR (L(0) AND COUNTER_BEGIN(11).LFBK)
	OR (M(1) AND M(2) AND COUNTER_BEGIN(11).LFBK)
	OR (NOT M(1) AND NOT M(2) AND NOT M(0))
	OR (NOT M(1) AND NOT L(0) AND NOT M(0)));

FDCPE_COUNTER_BEGIN12: FDCPE port map (COUNTER_BEGIN(12),COUNTER_BEGIN_D(12),CLK_4,'0','0');
COUNTER_BEGIN_D(12) <= ((L(0).LFBK AND NOT COUNTER_BEGIN(12).LFBK)
	OR (M(2).LFBK AND M(1).LFBK AND NOT COUNTER_BEGIN(12).LFBK)
	OR (NOT L(0).LFBK AND M(0).LFBK AND NOT M(1).LFBK)
	OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK));

FDCPE_COUNTER_BEGIN13: FDCPE port map (COUNTER_BEGIN(13),COUNTER_BEGIN_D(13),CLK_4,'0','0');
COUNTER_BEGIN_D(13) <= ((L(0).LFBK AND NOT COUNTER_BEGIN(13).LFBK)
	OR (M(2).LFBK AND M(1).LFBK AND NOT COUNTER_BEGIN(13).LFBK)
	OR (M(2).LFBK AND NOT L(0).LFBK AND M(0).LFBK AND NOT M(1).LFBK)
	OR (NOT M(2).LFBK AND L(0).LFBK AND NOT M(0).LFBK AND NOT M(1).LFBK));

FDCPE_COUNTER_BEGIN14: FDCPE port map (COUNTER_BEGIN(14),COUNTER_BEGIN_D(14),CLK_4,'0','0');
COUNTER_BEGIN_D(14) <= ((EXP0_.EXP)
	OR (M(1) AND M(2) AND COUNTER_BEGIN(14).LFBK)
	OR (M(1) AND L(0) AND COUNTER_BEGIN(14).LFBK));











FDCPE_L0: FDCPE port map (L(0),L_D(0),CLK_4,'0','0');
L_D(0) <= (NOT LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND 
	NOT LOOP_CNT(3).LFBK AND NOT LOOP_CNT(4).LFBK);

FTCPE_LOOP_CNT0: FTCPE port map (LOOP_CNT(0),'1',CLK_4,'0','0');

FTCPE_LOOP_CNT1: FTCPE port map (LOOP_CNT(1),LOOP_CNT(0),CLK_4,'0','0');

FTCPE_LOOP_CNT2: FTCPE port map (LOOP_CNT(2),LOOP_CNT_T(2),CLK_4,'0','0');
LOOP_CNT_T(2) <= (LOOP_CNT(0) AND LOOP_CNT(1).LFBK);

FTCPE_LOOP_CNT3: FTCPE port map (LOOP_CNT(3),LOOP_CNT_T(3),CLK_4,'0','0');
LOOP_CNT_T(3) <= (LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND 
	LOOP_CNT(2).LFBK);

FTCPE_LOOP_CNT4: FTCPE port map (LOOP_CNT(4),LOOP_CNT_T(4),CLK_4,'0','0');
LOOP_CNT_T(4) <= (LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND 
	LOOP_CNT(2).LFBK AND LOOP_CNT(3).LFBK);

FDCPE_M0: FDCPE port map (M(0),M_D(0),CLK_4,'0','0');
M_D(0) <= ((LOOP_CNT(2).LFBK AND LOOP_CNT(4).LFBK)
	OR (LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK)
	OR (NOT LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND 
	LOOP_CNT(4).LFBK)
	OR (NOT LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND 
	NOT LOOP_CNT(3).LFBK));

FDCPE_M1: FDCPE port map (M(1),M_D(1),CLK_4,'0','0');
M_D(1) <= ((EXP4_.EXP)
	OR (LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND 
	NOT LOOP_CNT(3).LFBK)
	OR (LOOP_CNT(2).LFBK AND NOT LOOP_CNT(3).LFBK AND 
	LOOP_CNT(4).LFBK)
	OR (LOOP_CNT(0) AND LOOP_CNT(1).LFBK AND 
	NOT LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK)
	OR (LOOP_CNT(0) AND NOT LOOP_CNT(1).LFBK AND 
	LOOP_CNT(3).LFBK AND NOT LOOP_CNT(4).LFBK));

FDCPE_M2: FDCPE port map (M(2),M_D(2),CLK_4,'0','0');
M_D(2) <= ((NOT LOOP_CNT(0) AND NOT LOOP_CNT(2).LFBK AND 
	NOT LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK)
	OR (LOOP_CNT(1).LFBK AND LOOP_CNT(2).LFBK AND 
	LOOP_CNT(3).LFBK AND NOT LOOP_CNT(4).LFBK)
	OR (NOT LOOP_CNT(1).LFBK AND NOT LOOP_CNT(2).LFBK AND 
	NOT LOOP_CNT(3).LFBK AND LOOP_CNT(4).LFBK));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


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 | 12                                                          74 | 
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 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
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 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              43 TIE                           
  2 TIE                              44 TIE                           
  3 TIE                              45 TIE                           
  4 TIE                              46 TIE                           
  5 TIE                              47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 CLK                              51 TIE                           
 10 TIE                              52 TIE                           
 11 TIE                              53 TIE                           
 12 TIE                              54 TIE                           
 13 TIE                              55 TIE                           
 14 TIE                              56 TIE                           
 15 TIE                              57 TIE                           
 16 GND                              58 TIE                           
 17 TIE                              59 TDO                           
 18 TIE                              60 GND                           
 19 BZ_OUT                           61 TIE                           
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 TIE                           
 24 TIE                              66 TIE                           
 25 TIE                              67 TIE                           
 26 TIE                              68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 TIE                           
 29 TMS                              71 TIE                           
 30 TCK                              72 TIE                           
 31 TIE                              73 VCC                           
 32 TIE                              74 TIE                           
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 TIE                           
 40 TIE                              82 TIE                           
 41 TIE                              83 TIE                           
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25