Equations

********** Mapped Logic **********
FDCPE_F0: FDCPE port map (F(0),'0','0',code_1_code(0)/code_1_code(0)_RSTF.LFBK,code_1_code(0)/code_1_code(0)_SETF.LFBK);
FDCPE_F1: FDCPE port map (F(1),'0','0',code_1_code(1)/code_1_code(1)_RSTF.LFBK,code_1_code(1)/code_1_code(1)_SETF.LFBK);
code_1_code(0)/code_1_code(0)_SETF <= ((I(1) AND I(0) AND NOT I(3) AND I(2))
      OR (NOT I(1) AND I(0) AND I(3) AND I(2)));
code_1_code(0)/code_1_code(0)_RSTF <= ((I(1) AND I(0) AND I(3) AND NOT I(2))
      OR (I(1) AND NOT I(0) AND I(3) AND I(2)));
code_1_code(1)/code_1_code(1)_SETF <= ((I(1) AND I(0) AND I(3) AND NOT I(2))
      OR (I(1) AND I(0) AND NOT I(3) AND I(2)));
code_1_code(1)/code_1_code(1)_RSTF <= ((I(1) AND NOT I(0) AND I(3) AND I(2))
      OR (NOT I(1) AND I(0) AND I(3) AND I(2)));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);