cpldfit: version J.30 Xilinx Inc. Fitter Report Design Name: PWM_DF Date: 4-30-2010, 10:29AM Device Used: XC95108-10-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 57 /108 ( 53%) 129 /540 ( 24%) 84 /216 ( 39%) 47 /108 ( 44%) 4 /69 ( 6%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 16/18 20/36 20 29/90 0/12 FB2 16/18 27/36 27 47/90 0/12 FB3 16/18 28/36 28 46/90 1/12 FB4 9/18 9/36 9 7/90 0/11 FB5 0/18 0/36 0 0/90 0/11 FB6 0/18 0/36 0 0/90 0/11 ----- ----- ----- ----- 57/108 84/216 129/540 1/69 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 2 2 | I/O : 3 63 Output : 1 1 | GCK/IO : 1 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 4 4 ** Power Data ** There are 57 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 1 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State PWM_OUT 24 26 FB3_8 19 I/O O STD FAST RESET ** 56 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State CNT<9> 1 9 FB1_3 STD RESET CNT<18> 1 18 FB1_4 STD RESET CNT<15> 1 15 FB1_5 STD RESET CNT<11> 1 11 FB1_6 STD RESET CNT<10> 1 10 FB1_7 STD RESET CLK_16 1 20 FB1_8 STD RESET CNT<8> 2 20 FB1_9 STD RESET CNT<7> 2 20 FB1_10 STD RESET CNT<5> 2 20 FB1_11 STD RESET CNT<19> 2 20 FB1_12 STD RESET CNT<17> 2 20 FB1_13 STD RESET CNT<16> 2 20 FB1_14 STD RESET CNT<14> 2 20 FB1_15 STD RESET CNT<13> 2 20 FB1_16 STD RESET CNT<12> 2 20 FB1_17 STD RESET CNT<4> 5 20 FB1_18 STD RESET Mcompar_PWM_OUT_cmp_lt0000_ALB29/Mcompar_PWM_OUT_cmp_lt0000_ALB29_D2 11 7 FB2_1 STD COUNT<9> 1 9 FB2_2 STD RESET COUNT<8> 1 8 FB2_4 STD RESET COUNT<7> 1 7 FB2_5 STD RESET COUNT<6> 1 6 FB2_6 STD RESET COUNT<5> 1 5 FB2_7 STD RESET COUNT<4> 1 4 FB2_8 STD RESET PWM_CNT<0> 2 3 FB2_9 STD RESET PWM_CNT<7> 3 10 FB2_10 STD RESET PWM_CNT<6> 3 9 FB2_11 STD RESET PWM_CNT<5> 3 8 FB2_12 STD RESET PWM_CNT<4> 3 7 FB2_13 STD RESET PWM_CNT<3> 3 6 FB2_14 STD RESET PWM_CNT<2> 3 5 FB2_15 STD RESET PWM_CNT<1> 3 4 FB2_16 STD RESET SF0/SF0_D2 7 6 FB2_17 STD COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 1 10 FB3_1 STD COUNT<16> 1 16 FB3_2 STD RESET COUNT<15> 1 15 FB3_3 STD RESET COUNT<14> 1 14 FB3_4 STD RESET COUNT<13> 1 13 FB3_5 STD RESET COUNT<12> 1 12 FB3_9 STD RESET COUNT<11> 1 11 FB3_10 STD RESET COUNT<10> 1 10 FB3_11 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$FX_DC$399 2 17 FB3_12 STD $OpTx$FX_DC$398 2 16 FB3_13 STD $OpTx$FX_DC$396 2 15 FB3_14 STD $OpTx$FX_DC$393 2 14 FB3_15 STD $OpTx$FX_DC$392 2 13 FB3_16 STD $OpTx$FX_DC$391 2 12 FB3_17 STD $OpTx$FX_DC$389 2 10 FB3_18 STD COUNT<3> 1 3 FB4_10 STD RESET COUNT<2> 1 2 FB4_11 STD RESET COUNT<1> 1 1 FB4_12 STD RESET COUNT<0> 0 0 FB4_13 STD RESET CNT<6> 1 6 FB4_14 STD RESET CNT<3> 1 3 FB4_15 STD RESET CNT<2> 1 2 FB4_16 STD RESET CNT<1> 1 1 FB4_17 STD RESET CNT<0> 0 0 FB4_18 STD RESET ** 3 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK FB1_12 9 GCK/I/O GCK K1 FB5_6 35 I/O I K0 FB5_8 36 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 20/16 Number of signals used by logic mapping into function block: 20 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O CNT<9> 1 0 0 4 FB1_3 2 I/O (b) CNT<18> 1 0 0 4 FB1_4 (b) (b) CNT<15> 1 0 0 4 FB1_5 3 I/O (b) CNT<11> 1 0 0 4 FB1_6 4 I/O (b) CNT<10> 1 0 0 4 FB1_7 (b) (b) CLK_16 1 0 0 4 FB1_8 5 I/O (b) CNT<8> 2 0 0 3 FB1_9 6 I/O (b) CNT<7> 2 0 0 3 FB1_10 (b) (b) CNT<5> 2 0 0 3 FB1_11 7 I/O (b) CNT<19> 2 0 0 3 FB1_12 9 GCK/I/O GCK CNT<17> 2 0 0 3 FB1_13 (b) (b) CNT<16> 2 0 0 3 FB1_14 10 GCK/I/O (b) CNT<14> 2 0 0 3 FB1_15 11 I/O (b) CNT<13> 2 0 0 3 FB1_16 12 GCK/I/O (b) CNT<12> 2 0 0 3 FB1_17 13 I/O (b) CNT<4> 5 0 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: CNT<0> 8: CNT<16>.LFBK 15: CNT<4>.LFBK 2: CNT<10>.LFBK 9: CNT<17>.LFBK 16: CNT<5>.LFBK 3: CNT<11>.LFBK 10: CNT<18>.LFBK 17: CNT<6> 4: CNT<12>.LFBK 11: CNT<19>.LFBK 18: CNT<7>.LFBK 5: CNT<13>.LFBK 12: CNT<1> 19: CNT<8>.LFBK 6: CNT<14>.LFBK 13: CNT<2> 20: CNT<9>.LFBK 7: CNT<15>.LFBK 14: CNT<3> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CNT<9> X..........XXXXXXXX..................... 9 9 CNT<18> XXXXXXXXX..XXXXXXXXX.................... 18 18 CNT<15> XXXXXX.....XXXXXXXXX.................... 15 15 CNT<11> XX.........XXXXXXXXX.................... 11 11 CNT<10> X..........XXXXXXXXX.................... 10 10 CLK_16 XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<8> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<7> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<5> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<19> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<17> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<16> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<14> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<13> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<12> XXXXXXXXXXXXXXXXXXXX.................... 20 20 CNT<4> XXXXXXXXXXXXXXXXXXXX.................... 20 20 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 27/9 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use Mcompar_PWM_OUT_cmp_lt0000_ALB29/Mcompar_PWM_OUT_cmp_lt0000_ALB29_D2 11 6<- 0 0 FB2_1 (b) (b) COUNT<9> 1 0 /\1 3 FB2_2 71 I/O (b) (unused) 0 0 0 5 FB2_3 72 I/O COUNT<8> 1 0 0 4 FB2_4 (b) (b) COUNT<7> 1 0 0 4 FB2_5 74 GSR/I/O (b) COUNT<6> 1 0 0 4 FB2_6 75 I/O (b) COUNT<5> 1 0 0 4 FB2_7 (b) (b) COUNT<4> 1 0 0 4 FB2_8 76 GTS/I/O (b) PWM_CNT<0> 2 0 0 3 FB2_9 77 GTS/I/O (b) PWM_CNT<7> 3 0 0 2 FB2_10 (b) (b) PWM_CNT<6> 3 0 0 2 FB2_11 79 I/O (b) PWM_CNT<5> 3 0 0 2 FB2_12 80 I/O (b) PWM_CNT<4> 3 0 0 2 FB2_13 (b) (b) PWM_CNT<3> 3 0 0 2 FB2_14 81 I/O (b) PWM_CNT<2> 3 0 0 2 FB2_15 82 I/O (b) PWM_CNT<1> 3 0 \/2 0 FB2_16 83 I/O (b) SF0/SF0_D2 7 2<- 0 0 FB2_17 84 I/O (b) (unused) 0 0 \/5 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$389 10: COUNT<2> 19: K1 2: $OpTx$FX_DC$391 11: COUNT<3> 20: PWM_CNT<0>.LFBK 3: $OpTx$FX_DC$396 12: COUNT<4>.LFBK 21: PWM_CNT<1>.LFBK 4: $OpTx$FX_DC$398 13: COUNT<5>.LFBK 22: PWM_CNT<2>.LFBK 5: $OpTx$FX_DC$399 14: COUNT<6>.LFBK 23: PWM_CNT<3>.LFBK 6: CLK_16 15: COUNT<7>.LFBK 24: PWM_CNT<4>.LFBK 7: COUNT<0> 16: COUNT<8>.LFBK 25: PWM_CNT<5>.LFBK 8: COUNT<10> 17: COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 26: PWM_CNT<6>.LFBK 9: COUNT<1> 18: K0 27: PWM_CNT<7>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Mcompar_PWM_OUT_cmp_lt0000_ALB29/Mcompar_PWM_OUT_cmp_lt0000_ALB29_D2 XX.....X........X..XXX.................. 7 7 COUNT<9> ......X.XXXXXXXX........................ 9 9 COUNT<8> ......X.XXXXXXX......................... 8 8 COUNT<7> ......X.XXXXXX.......................... 7 7 COUNT<6> ......X.XXXXX........................... 6 6 COUNT<5> ......X.XXXX............................ 5 5 COUNT<4> ......X.XXX............................. 4 4 PWM_CNT<0> .....X...........XX..................... 3 3 PWM_CNT<7> .....X...........XXXXXXXXX.............. 10 10 PWM_CNT<6> .....X...........XXXXXXXX............... 9 9 PWM_CNT<5> .....X...........XXXXXXX................ 8 8 PWM_CNT<4> .....X...........XXXXXX................. 7 7 PWM_CNT<3> .....X...........XXXXX.................. 6 6 PWM_CNT<2> .....X...........XXXX................... 5 5 PWM_CNT<1> .....X...........XXX.................... 4 4 SF0/SF0_D2 ..XXX...................XXX............. 6 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 28/8 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 1 0 0 4 FB3_1 (b) (b) COUNT<16> 1 0 0 4 FB3_2 14 I/O (b) COUNT<15> 1 0 0 4 FB3_3 15 I/O (b) COUNT<14> 1 0 0 4 FB3_4 (b) (b) COUNT<13> 1 0 \/4 0 FB3_5 17 I/O (b) (unused) 0 0 \/5 0 FB3_6 18 I/O (b) (unused) 0 0 \/5 0 FB3_7 (b) (b) PWM_OUT 24 19<- 0 0 FB3_8 19 I/O O COUNT<12> 1 1<- /\5 0 FB3_9 20 I/O (b) COUNT<11> 1 0 /\1 3 FB3_10 (b) (b) COUNT<10> 1 0 0 4 FB3_11 21 I/O (b) $OpTx$FX_DC$399 2 0 0 3 FB3_12 23 I/O (b) $OpTx$FX_DC$398 2 0 0 3 FB3_13 (b) (b) $OpTx$FX_DC$396 2 0 0 3 FB3_14 24 I/O (b) $OpTx$FX_DC$393 2 0 0 3 FB3_15 25 I/O (b) $OpTx$FX_DC$392 2 0 0 3 FB3_16 26 I/O (b) $OpTx$FX_DC$391 2 0 0 3 FB3_17 31 I/O (b) $OpTx$FX_DC$389 2 0 0 3 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$392.LFBK 11: COUNT<15>.LFBK 20: COUNT<8> 2: $OpTx$FX_DC$393.LFBK 12: COUNT<16>.LFBK 21: COUNT<9> 3: $OpTx$FX_DC$398.LFBK 13: COUNT<1> 22: Mcompar_PWM_OUT_cmp_lt0000_ALB29/Mcompar_PWM_OUT_cmp_lt0000_ALB29_D2 4: $OpTx$FX_DC$399.LFBK 14: COUNT<2> 23: PWM_CNT<3> 5: COUNT<0> 15: COUNT<3> 24: PWM_CNT<4> 6: COUNT<10>.LFBK 16: COUNT<4> 25: PWM_CNT<5> 7: COUNT<11>.LFBK 17: COUNT<5> 26: PWM_CNT<6> 8: COUNT<12>.LFBK 18: COUNT<6> 27: PWM_CNT<7> 9: COUNT<13>.LFBK 19: COUNT<7> 28: SF0/SF0_D2 10: COUNT<14>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 ....X.......XXXXXXXXX................... 10 10 COUNT<16> ....XXXXXXX.XXXXXXXXX................... 16 16 COUNT<15> ....XXXXXX..XXXXXXXXX................... 15 15 COUNT<14> ....XXXXX...XXXXXXXXX................... 14 14 COUNT<13> ....XXXX....XXXXXXXXX................... 13 13 PWM_OUT XXXXXXXXXX..XXXXXXXXXXXXXXXX............ 26 26 COUNT<12> ....XXX.....XXXXXXXXX................... 12 12 COUNT<11> ....XX......XXXXXXXXX................... 11 11 COUNT<10> ....X.......XXXXXXXXX................... 10 10 $OpTx$FX_DC$399 ....XXXXXXXXXXXXXXXXX................... 17 17 $OpTx$FX_DC$398 ....XXXXXXX.XXXXXXXXX................... 16 16 $OpTx$FX_DC$396 ....XXXXXX..XXXXXXXXX................... 15 15 $OpTx$FX_DC$393 ....XXXXX...XXXXXXXXX................... 14 14 $OpTx$FX_DC$392 ....XXXX....XXXXXXXXX................... 13 13 $OpTx$FX_DC$391 ....XXX.....XXXXXXXXX................... 12 12 $OpTx$FX_DC$389 ....X.......XXXXXXXXX................... 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 9/27 Number of signals used by logic mapping into function block: 9 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 57 I/O (unused) 0 0 0 5 FB4_3 58 I/O (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 61 I/O (unused) 0 0 0 5 FB4_6 62 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 63 I/O (unused) 0 0 0 5 FB4_9 65 I/O COUNT<3> 1 0 0 4 FB4_10 (b) (b) COUNT<2> 1 0 0 4 FB4_11 66 I/O (b) COUNT<1> 1 0 0 4 FB4_12 67 I/O (b) COUNT<0> 0 0 0 5 FB4_13 (b) (b) CNT<6> 1 0 0 4 FB4_14 68 I/O (b) CNT<3> 1 0 0 4 FB4_15 69 I/O (b) CNT<2> 1 0 0 4 FB4_16 (b) (b) CNT<1> 1 0 0 4 FB4_17 70 I/O (b) CNT<0> 0 0 0 5 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: CNT<0>.LFBK 4: CNT<3>.LFBK 7: COUNT<0>.LFBK 2: CNT<1>.LFBK 5: CNT<4> 8: COUNT<1>.LFBK 3: CNT<2>.LFBK 6: CNT<5> 9: COUNT<2>.LFBK Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs COUNT<3> ......XXX............................... 3 3 COUNT<2> ......XX................................ 2 2 COUNT<1> ......X................................. 1 1 COUNT<0> ........................................ 0 0 CNT<6> XXXXXX.................................. 6 6 CNT<3> XXX..................................... 3 3 CNT<2> XX...................................... 2 2 CNT<1> X....................................... 1 1 CNT<0> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 0/36 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) (unused) 0 0 0 5 FB5_2 32 I/O (unused) 0 0 0 5 FB5_3 33 I/O (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 34 I/O (unused) 0 0 0 5 FB5_6 35 I/O I (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 36 I/O I (unused) 0 0 0 5 FB5_9 37 I/O (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 39 I/O (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 41 I/O (unused) 0 0 0 5 FB5_15 43 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O (unused) 0 0 0 5 FB5_18 (b) *********************************** FB6 *********************************** Number of function block inputs used/remaining: 0/36 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 45 I/O (unused) 0 0 0 5 FB6_3 46 I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 47 I/O (unused) 0 0 0 5 FB6_6 48 I/O (unused) 0 0 0 5 FB6_7 (b) (unused) 0 0 0 5 FB6_8 50 I/O (unused) 0 0 0 5 FB6_9 51 I/O (unused) 0 0 0 5 FB6_10 (b) (unused) 0 0 0 5 FB6_11 52 I/O (unused) 0 0 0 5 FB6_12 53 I/O (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 54 I/O (unused) 0 0 0 5 FB6_15 55 I/O (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 56 I/O (unused) 0 0 0 5 FB6_18 (b) ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$389 <= NOT (COUNT(9) XOR $OpTx$FX_DC$389 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8))); $OpTx$FX_DC$391 <= NOT (COUNT(11).LFBK XOR $OpTx$FX_DC$391 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK)); $OpTx$FX_DC$392 <= NOT (COUNT(12).LFBK XOR $OpTx$FX_DC$392 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK)); $OpTx$FX_DC$393 <= NOT (COUNT(13).LFBK XOR $OpTx$FX_DC$393 <= NOT ((COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK)); $OpTx$FX_DC$396 <= COUNT(14).LFBK XOR $OpTx$FX_DC$396 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK AND COUNT(13).LFBK); $OpTx$FX_DC$398 <= COUNT(15).LFBK XOR $OpTx$FX_DC$398 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND COUNT(12).LFBK AND COUNT(13).LFBK); $OpTx$FX_DC$399 <= COUNT(16).LFBK XOR $OpTx$FX_DC$399 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND COUNT(12).LFBK AND COUNT(13).LFBK AND COUNT(15).LFBK); FTCPE_CLK_16: FTCPE port map (CLK_16,CLK_16_T,CLK,'0','0'); CLK_16_T <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK); FTCPE_CNT0: FTCPE port map (CNT(0),'1',CLK,'0','0'); FTCPE_CNT1: FTCPE port map (CNT(1),CNT(0).LFBK,CLK,'0','0'); FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),CLK,'0','0'); CNT_T(2) <= (CNT(0).LFBK AND CNT(1).LFBK); FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),CLK,'0','0'); CNT_T(3) <= (CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK); FTCPE_CNT4: FTCPE port map (CNT(4),CNT_T(4),CLK,'0','0'); CNT_T(4) <= ((NOT CNT(0)) OR (NOT CNT(1)) OR (NOT CNT(2)) OR (NOT CNT(3)) OR (NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT5: FTCPE port map (CNT(5),CNT_T(5),CLK,'0','0'); CNT_T(5) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(4).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT6: FTCPE port map (CNT(6),CNT_T(6),CLK,'0','0'); CNT_T(6) <= (CNT(4) AND CNT(5) AND CNT(0).LFBK AND CNT(1).LFBK AND CNT(2).LFBK AND CNT(3).LFBK); FTCPE_CNT7: FTCPE port map (CNT(7),CNT_T(7),CLK,'0','0'); CNT_T(7) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(4).LFBK AND CNT(5).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT8: FTCPE port map (CNT(8),CNT_T(8),CLK,'0','0'); CNT_T(8) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT9: FTCPE port map (CNT(9),CNT_T(9),CLK,'0','0'); CNT_T(9) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK); FTCPE_CNT10: FTCPE port map (CNT(10),CNT_T(10),CLK,'0','0'); CNT_T(10) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK); FTCPE_CNT11: FTCPE port map (CNT(11),CNT_T(11),CLK,'0','0'); CNT_T(11) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK); FTCPE_CNT12: FTCPE port map (CNT(12),CNT_T(12),CLK,'0','0'); CNT_T(12) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT13: FTCPE port map (CNT(13),CNT_T(13),CLK,'0','0'); CNT_T(13) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT14: FTCPE port map (CNT(14),CNT_T(14),CLK,'0','0'); CNT_T(14) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT15: FTCPE port map (CNT(15),CNT_T(15),CLK,'0','0'); CNT_T(15) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK); FTCPE_CNT16: FTCPE port map (CNT(16),CNT_T(16),CLK,'0','0'); CNT_T(16) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT17: FTCPE port map (CNT(17),CNT_T(17),CLK,'0','0'); CNT_T(17) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_CNT18: FTCPE port map (CNT(18),CNT_T(18),CLK,'0','0'); CNT_T(18) <= (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK); FTCPE_CNT19: FTCPE port map (CNT(19),CNT_T(19),CLK,'0','0'); CNT_T(19) <= ((CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND CNT(6) AND CNT(10).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND CNT(18).LFBK AND CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND CNT(9).LFBK) OR (CNT(0) AND CNT(1) AND CNT(2) AND CNT(3) AND NOT CNT(6) AND NOT CNT(10).LFBK AND NOT CNT(11).LFBK AND CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK AND NOT CNT(15).LFBK AND CNT(16).LFBK AND CNT(17).LFBK AND NOT CNT(18).LFBK AND NOT CNT(4).LFBK AND CNT(5).LFBK AND CNT(7).LFBK AND CNT(8).LFBK AND NOT CNT(9).LFBK AND CNT(19).LFBK)); FTCPE_COUNT0: FTCPE port map (COUNT(0),'1',CLK,'0','0'); FTCPE_COUNT1: FTCPE port map (COUNT(1),COUNT(0).LFBK,CLK,'0','0'); FTCPE_COUNT2: FTCPE port map (COUNT(2),COUNT_T(2),CLK,'0','0'); COUNT_T(2) <= (COUNT(0).LFBK AND COUNT(1).LFBK); FTCPE_COUNT3: FTCPE port map (COUNT(3),COUNT_T(3),CLK,'0','0'); COUNT_T(3) <= (COUNT(0).LFBK AND COUNT(1).LFBK AND COUNT(2).LFBK); FTCPE_COUNT4: FTCPE port map (COUNT(4),COUNT_T(4),CLK,'0','0'); COUNT_T(4) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3)); FTCPE_COUNT5: FTCPE port map (COUNT(5),COUNT_T(5),CLK,'0','0'); COUNT_T(5) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4).LFBK); FTCPE_COUNT6: FTCPE port map (COUNT(6),COUNT_T(6),CLK,'0','0'); COUNT_T(6) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4).LFBK AND COUNT(5).LFBK); FTCPE_COUNT7: FTCPE port map (COUNT(7),COUNT_T(7),CLK,'0','0'); COUNT_T(7) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4).LFBK AND COUNT(5).LFBK AND COUNT(6).LFBK); FTCPE_COUNT8: FTCPE port map (COUNT(8),COUNT_T(8),CLK,'0','0'); COUNT_T(8) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4).LFBK AND COUNT(5).LFBK AND COUNT(6).LFBK AND COUNT(7).LFBK); FTCPE_COUNT9: FTCPE port map (COUNT(9),COUNT_T(9),CLK,'0','0'); COUNT_T(9) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4).LFBK AND COUNT(5).LFBK AND COUNT(6).LFBK AND COUNT(7).LFBK AND COUNT(8).LFBK); FTCPE_COUNT10: FTCPE port map (COUNT(10),COUNT_T(10),CLK,'0','0'); COUNT_T(10) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9)); FTCPE_COUNT11: FTCPE port map (COUNT(11),COUNT_T(11),CLK,'0','0'); COUNT_T(11) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK); FTCPE_COUNT12: FTCPE port map (COUNT(12),COUNT(11).EXP,CLK,'0','0'); FTCPE_COUNT13: FTCPE port map (COUNT(13),COUNT_T(13),CLK,'0','0'); COUNT_T(13) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK); FTCPE_COUNT14: FTCPE port map (COUNT(14),COUNT_T(14),CLK,'0','0'); COUNT_T(14) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(12).LFBK AND COUNT(13).LFBK); FTCPE_COUNT15: FTCPE port map (COUNT(15),COUNT_T(15),CLK,'0','0'); COUNT_T(15) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND COUNT(12).LFBK AND COUNT(13).LFBK); FTCPE_COUNT16: FTCPE port map (COUNT(16),COUNT_T(16),CLK,'0','0'); COUNT_T(16) <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9) AND COUNT(10).LFBK AND COUNT(11).LFBK AND COUNT(14).LFBK AND COUNT(12).LFBK AND COUNT(13).LFBK AND COUNT(15).LFBK); COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 <= (COUNT(0) AND COUNT(1) AND COUNT(2) AND COUNT(3) AND COUNT(4) AND COUNT(5) AND COUNT(6) AND COUNT(7) AND COUNT(8) AND COUNT(9)); Mcompar_PWM_OUT_cmp_lt0000_ALB29/Mcompar_PWM_OUT_cmp_lt0000_ALB29_D2 <= ((COUNT(9).EXP) OR (EXP0_.EXP) OR ($OpTx$FX_DC$391 AND PWM_CNT(2).LFBK) OR (COUNT(10) AND COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK) OR (NOT COUNT(10) AND NOT COUNT_Madd__add0000__and0008/COUNT_Madd__add0000__and0008_D2 AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK) OR ($OpTx$FX_DC$389 AND $OpTx$FX_DC$391 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK) OR ($OpTx$FX_DC$389 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK)); FTCPE_PWM_CNT0: FTCPE port map (PWM_CNT(0),PWM_CNT_T(0),CLK_16,'0','0'); PWM_CNT_T(0) <= (K1 AND K0); FTCPE_PWM_CNT1: FTCPE port map (PWM_CNT(1),PWM_CNT_T(1),CLK_16,'0','0'); PWM_CNT_T(1) <= ((NOT K0 AND PWM_CNT(0).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK)); FTCPE_PWM_CNT2: FTCPE port map (PWM_CNT(2),PWM_CNT_T(2),CLK_16,'0','0'); PWM_CNT_T(2) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK)); FTCPE_PWM_CNT3: FTCPE port map (PWM_CNT(3),PWM_CNT_T(3),CLK_16,'0','0'); PWM_CNT_T(3) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND NOT PWM_CNT(2).LFBK)); FTCPE_PWM_CNT4: FTCPE port map (PWM_CNT(4),PWM_CNT_T(4),CLK_16,'0','0'); PWM_CNT_T(4) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK)); FTCPE_PWM_CNT5: FTCPE port map (PWM_CNT(5),PWM_CNT_T(5),CLK_16,'0','0'); PWM_CNT_T(5) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK AND PWM_CNT(4).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK AND NOT PWM_CNT(4).LFBK)); FTCPE_PWM_CNT6: FTCPE port map (PWM_CNT(6),PWM_CNT_T(6),CLK_16,'0','0'); PWM_CNT_T(6) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK AND PWM_CNT(4).LFBK AND PWM_CNT(5).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK AND NOT PWM_CNT(4).LFBK AND NOT PWM_CNT(5).LFBK)); FTCPE_PWM_CNT7: FTCPE port map (PWM_CNT(7),PWM_CNT_T(7),CLK_16,'0','0'); PWM_CNT_T(7) <= ((NOT K0 AND PWM_CNT(0).LFBK AND PWM_CNT(1).LFBK AND PWM_CNT(2).LFBK AND PWM_CNT(3).LFBK AND PWM_CNT(4).LFBK AND PWM_CNT(5).LFBK AND PWM_CNT(6).LFBK) OR (NOT K1 AND K0 AND NOT PWM_CNT(0).LFBK AND NOT PWM_CNT(1).LFBK AND NOT PWM_CNT(2).LFBK AND NOT PWM_CNT(3).LFBK AND NOT PWM_CNT(4).LFBK AND NOT PWM_CNT(5).LFBK AND NOT PWM_CNT(6).LFBK)); FDCPE_PWM_OUT: FDCPE port map (PWM_OUT,PWM_OUT_D,CLK,'0','0'); PWM_OUT_D <= ((EXP2_.EXP) OR (COUNT(12).EXP) OR (PWM_CNT(4) AND NOT SF0/SF0_D2 AND $OpTx$FX_DC$393.LFBK) OR (PWM_CNT(6) AND NOT SF0/SF0_D2 AND NOT $OpTx$FX_DC$398.LFBK) OR (PWM_CNT(7) AND NOT SF0/SF0_D2 AND NOT $OpTx$FX_DC$399.LFBK) OR (PWM_CNT(5) AND NOT COUNT(0) AND NOT SF0/SF0_D2 AND NOT COUNT(14).LFBK) OR (PWM_CNT(5) AND NOT COUNT(1) AND NOT SF0/SF0_D2 AND NOT COUNT(14).LFBK)); SF0/SF0_D2 <= ((PWM_CNT(1).EXP) OR ($OpTx$FX_DC$399 AND NOT PWM_CNT(7).LFBK) OR ($OpTx$FX_DC$398 AND $OpTx$FX_DC$399 AND NOT PWM_CNT(6).LFBK) OR ($OpTx$FX_DC$398 AND NOT PWM_CNT(6).LFBK AND NOT PWM_CNT(7).LFBK) OR ($OpTx$FX_DC$398 AND $OpTx$FX_DC$396 AND NOT PWM_CNT(5).LFBK AND NOT PWM_CNT(7).LFBK) OR ($OpTx$FX_DC$396 AND NOT PWM_CNT(5).LFBK AND NOT PWM_CNT(6).LFBK AND NOT PWM_CNT(7).LFBK)); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-10-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-10-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 43 TIE 2 TIE 44 TIE 3 TIE 45 TIE 4 TIE 46 TIE 5 TIE 47 TIE 6 TIE 48 TIE 7 TIE 49 GND 8 GND 50 TIE 9 CLK 51 TIE 10 TIE 52 TIE 11 TIE 53 TIE 12 TIE 54 TIE 13 TIE 55 TIE 14 TIE 56 TIE 15 TIE 57 TIE 16 GND 58 TIE 17 TIE 59 TDO 18 TIE 60 GND 19 PWM_OUT 61 TIE 20 TIE 62 TIE 21 TIE 63 TIE 22 VCC 64 VCC 23 TIE 65 TIE 24 TIE 66 TIE 25 TIE 67 TIE 26 TIE 68 TIE 27 GND 69 TIE 28 TDI 70 TIE 29 TMS 71 TIE 30 TCK 72 TIE 31 TIE 73 VCC 32 TIE 74 TIE 33 TIE 75 TIE 34 TIE 76 TIE 35 K1 77 TIE 36 K0 78 VCC 37 TIE 79 TIE 38 VCC 80 TIE 39 TIE 81 TIE 40 TIE 82 TIE 41 TIE 83 TIE 42 GND 84 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-10-PC84 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25