Timing Report

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Design Name CPLD_MUSIC
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Wed Apr 28 16:15:01 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'MUSIC_OUT.CLKF' has multiple original clock nets 'COUNTER<0>.Q' 'COUNTER<10>.Q' 'COUNTER<9>.Q' 'COUNTER<8>.Q' 'COUNTER<7>.Q' 'COUNTER<6>.Q' 'COUNTER<5>.Q' 'COUNTER<4>.Q' 'COUNTER<3>.Q' 'COUNTER<2>.Q' 'COUNTER<1>.Q'.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for ALE
Clock to Setup (tCYC) 10.000 ns.
Pad to Pad Delay (tPD) 10.000 ns.
Setup to Clock at the Pad (tSU) 2.000 ns.
Clock Pad to Output Pad Delay (tCO) 26.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
TS1015 0.0 0.0 0 0
TS1016 0.0 0.0 0 0
TS1017 0.0 0.0 0 0
TS1018 0.0 0.0 0 0
TS1019 0.0 0.0 0 0
TS1020 0.0 0.0 0 0
TS1021 0.0 0.0 0 0
TS1022 0.0 0.0 0 0
TS1023 0.0 0.0 0 0
TS1024 0.0 0.0 0 0
TS1025 0.0 0.0 0 0
TS1026 0.0 0.0 0 0
AUTO_TS_F2F 0.0 15.0 214 214
AUTO_TS_P2P 0.0 26.0 14 14
AUTO_TS_P2F 0.0 8.5 39 39
AUTO_TS_F2P 0.0 16.5 6 6


Constraint: TS1000

Description: PERIOD:PERIOD_COUNTER_BEGIN<9>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_COUNTER_BEGIN<8>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_COUNTER_BEGIN<7>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_COUNTER_BEGIN<6>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_COUNTER_BEGIN<5>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_COUNTER_BEGIN<4>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_COUNTER_BEGIN<3>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_COUNTER_BEGIN<2>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_COUNTER_BEGIN<1>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_COUNTER_BEGIN<10>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_COUNTER_BEGIN<0>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_ALE:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_CLK_1M.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_RD:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1015

Description: PERIOD:PERIOD_WR:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1016

Description: PERIOD:PERIOD_COUNTER<0>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1017

Description: PERIOD:PERIOD_COUNTER<10>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1018

Description: PERIOD:PERIOD_COUNTER<9>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1019

Description: PERIOD:PERIOD_COUNTER<8>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1020

Description: PERIOD:PERIOD_COUNTER<7>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1021

Description: PERIOD:PERIOD_COUNTER<6>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1022

Description: PERIOD:PERIOD_COUNTER<5>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1023

Description: PERIOD:PERIOD_COUNTER<4>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1024

Description: PERIOD:PERIOD_COUNTER<3>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1025

Description: PERIOD:PERIOD_COUNTER<2>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1026

Description: PERIOD:PERIOD_COUNTER<1>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ADDRESS_REG<0>.Q to DATA_REG<0>.D 0.000 15.000 -15.000
ADDRESS_REG<0>.Q to DATA_REG<1>.D 0.000 15.000 -15.000
ADDRESS_REG<0>.Q to DATA_REG<2>.D 0.000 15.000 -15.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to MUSIC_OUT 0.000 26.000 -26.000
RD to DATA_PORT<0> 0.000 23.000 -23.000
RD to DATA_PORT<4> 0.000 23.000 -23.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DATA_PORT<0> to ADDRESS_REG<0>.D 0.000 8.500 -8.500
DATA_PORT<0> to DATA_REG<0>.D 0.000 8.500 -8.500
DATA_PORT<1> to ADDRESS_REG<1>.D 0.000 8.500 -8.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ACK_REG<0>.Q to DATA_PORT<0> 0.000 16.500 -16.500
ACK_REG<4>.Q to DATA_PORT<4> 0.000 16.500 -16.500
ACK_REG<5>.Q to DATA_PORT<5> 0.000 16.500 -16.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
ALE 83.333 Limited by Clock Pulse Width for ALE
CLK_1M.Q 83.333 Limited by Clock Pulse Width for CLK_1M.Q
RD 83.333 Limited by Clock Pulse Width for RD
CLK 111.111 Limited by Clock Pulse Width for CLK
WR 83.333 Limited by Clock Pulse Width for WR
COUNTER<0>.Q 83.333 Limited by Clock Pulse Width for COUNTER<0>.Q
COUNTER<10>.Q 83.333 Limited by Clock Pulse Width for COUNTER<10>.Q
COUNTER<9>.Q 83.333 Limited by Clock Pulse Width for COUNTER<9>.Q
COUNTER<8>.Q 83.333 Limited by Clock Pulse Width for COUNTER<8>.Q
COUNTER<7>.Q 83.333 Limited by Clock Pulse Width for COUNTER<7>.Q
COUNTER<6>.Q 83.333 Limited by Clock Pulse Width for COUNTER<6>.Q
COUNTER<5>.Q 83.333 Limited by Clock Pulse Width for COUNTER<5>.Q
COUNTER<4>.Q 83.333 Limited by Clock Pulse Width for COUNTER<4>.Q
COUNTER<3>.Q 83.333 Limited by Clock Pulse Width for COUNTER<3>.Q
COUNTER<2>.Q 83.333 Limited by Clock Pulse Width for COUNTER<2>.Q
COUNTER<1>.Q 83.333 Limited by Clock Pulse Width for COUNTER<1>.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock ALE
Source Pad Setup to clk (edge) Hold to clk (edge)
DATA_PORT<0> 2.000 1.500
DATA_PORT<1> 2.000 1.500
DATA_PORT<2> 2.000 1.500
DATA_PORT<3> 2.000 1.500
DATA_PORT<4> 2.000 1.500
DATA_PORT<5> 2.000 1.500
DATA_PORT<6> 2.000 1.500
DATA_PORT<7> 2.000 1.500

Setup/Hold Times for Clock WR
Source Pad Setup to clk (edge) Hold to clk (edge)
DATA_PORT<0> 2.000 1.500
DATA_PORT<1> 2.000 1.500
DATA_PORT<2> 2.000 1.500
DATA_PORT<3> 2.000 1.500
DATA_PORT<4> 2.000 1.500
DATA_PORT<5> 2.000 1.500
DATA_PORT<6> 2.000 1.500
DATA_PORT<7> 2.000 1.500


Clock to Pad Timing

Clock RD to Pad
Destination Pad Clock (edge) to Pad
DATA_PORT<0> 23.000
DATA_PORT<4> 23.000
DATA_PORT<5> 23.000
DATA_PORT<6> 23.000
DATA_PORT<7> 23.000

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
MUSIC_OUT 26.000


Clock to Setup Times for Clocks

Clock to Setup for clock CLK_1M.Q
Source Destination Delay
COUNTER<0>.Q COUNTER<6>.D 10.000
COUNTER<0>.Q COUNTER<7>.D 10.000
COUNTER<0>.Q COUNTER<8>.D 10.000
COUNTER<0>.Q COUNTER<9>.D 10.000
COUNTER<10>.Q COUNTER<2>.D 10.000
COUNTER<10>.Q COUNTER<3>.D 10.000
COUNTER<10>.Q COUNTER<4>.D 10.000
COUNTER<10>.Q COUNTER<5>.D 10.000
COUNTER<10>.Q COUNTER<6>.D 10.000
COUNTER<10>.Q COUNTER<7>.D 10.000
COUNTER<10>.Q COUNTER<8>.D 10.000
COUNTER<1>.Q COUNTER<2>.D 10.000
COUNTER<1>.Q COUNTER<3>.D 10.000
COUNTER<1>.Q COUNTER<6>.D 10.000
COUNTER<1>.Q COUNTER<7>.D 10.000
COUNTER<1>.Q COUNTER<8>.D 10.000
COUNTER<1>.Q COUNTER<9>.D 10.000
COUNTER<2>.Q COUNTER<2>.D 10.000
COUNTER<2>.Q COUNTER<3>.D 10.000
COUNTER<2>.Q COUNTER<6>.D 10.000
COUNTER<2>.Q COUNTER<7>.D 10.000
COUNTER<2>.Q COUNTER<8>.D 10.000
COUNTER<2>.Q COUNTER<9>.D 10.000
COUNTER<3>.Q COUNTER<2>.D 10.000
COUNTER<3>.Q COUNTER<3>.D 10.000
COUNTER<3>.Q COUNTER<4>.D 10.000
COUNTER<3>.Q COUNTER<5>.D 10.000
COUNTER<3>.Q COUNTER<6>.D 10.000
COUNTER<3>.Q COUNTER<7>.D 10.000
COUNTER<3>.Q COUNTER<8>.D 10.000
COUNTER<3>.Q COUNTER<9>.D 10.000
COUNTER<4>.Q COUNTER<2>.D 10.000
COUNTER<4>.Q COUNTER<3>.D 10.000
COUNTER<4>.Q COUNTER<4>.D 10.000
COUNTER<4>.Q COUNTER<5>.D 10.000
COUNTER<4>.Q COUNTER<6>.D 10.000
COUNTER<4>.Q COUNTER<7>.D 10.000
COUNTER<4>.Q COUNTER<8>.D 10.000
COUNTER<4>.Q COUNTER<9>.D 10.000
COUNTER<5>.Q COUNTER<2>.D 10.000
COUNTER<5>.Q COUNTER<3>.D 10.000
COUNTER<5>.Q COUNTER<4>.D 10.000
COUNTER<5>.Q COUNTER<5>.D 10.000
COUNTER<5>.Q COUNTER<6>.D 10.000
COUNTER<5>.Q COUNTER<7>.D 10.000
COUNTER<5>.Q COUNTER<8>.D 10.000
COUNTER<5>.Q COUNTER<9>.D 10.000
COUNTER<6>.Q COUNTER<2>.D 10.000
COUNTER<6>.Q COUNTER<3>.D 10.000
COUNTER<6>.Q COUNTER<4>.D 10.000
COUNTER<6>.Q COUNTER<5>.D 10.000
COUNTER<6>.Q COUNTER<7>.D 10.000
COUNTER<6>.Q COUNTER<8>.D 10.000
COUNTER<6>.Q COUNTER<9>.D 10.000
COUNTER<7>.Q COUNTER<2>.D 10.000
COUNTER<7>.Q COUNTER<3>.D 10.000
COUNTER<7>.Q COUNTER<4>.D 10.000
COUNTER<7>.Q COUNTER<5>.D 10.000
COUNTER<7>.Q COUNTER<8>.D 10.000
COUNTER<7>.Q COUNTER<9>.D 10.000
COUNTER<8>.Q COUNTER<2>.D 10.000
COUNTER<8>.Q COUNTER<3>.D 10.000
COUNTER<8>.Q COUNTER<4>.D 10.000
COUNTER<8>.Q COUNTER<5>.D 10.000
COUNTER<8>.Q COUNTER<9>.D 10.000
COUNTER<9>.Q COUNTER<2>.D 10.000
COUNTER<9>.Q COUNTER<3>.D 10.000
COUNTER<9>.Q COUNTER<4>.D 10.000
COUNTER<9>.Q COUNTER<5>.D 10.000
COUNTER<9>.Q COUNTER<7>.D 10.000
COUNTER<9>.Q COUNTER<8>.D 10.000
COUNTER<0>.Q COUNTER<0>.D 9.000
COUNTER<0>.Q COUNTER<10>.D 9.000
COUNTER<0>.Q COUNTER<1>.D 9.000
COUNTER<0>.Q COUNTER<2>.D 9.000
COUNTER<0>.Q COUNTER<3>.D 9.000
COUNTER<0>.Q COUNTER<4>.D 9.000
COUNTER<0>.Q COUNTER<5>.D 9.000
COUNTER<10>.Q COUNTER<0>.D 9.000
COUNTER<10>.Q COUNTER<10>.D 9.000
COUNTER<10>.Q COUNTER<1>.D 9.000
COUNTER<10>.Q COUNTER<9>.D 9.000
COUNTER<1>.Q COUNTER<0>.D 9.000
COUNTER<1>.Q COUNTER<10>.D 9.000
COUNTER<1>.Q COUNTER<1>.D 9.000
COUNTER<1>.Q COUNTER<4>.D 9.000
COUNTER<1>.Q COUNTER<5>.D 9.000
COUNTER<2>.Q COUNTER<0>.D 9.000
COUNTER<2>.Q COUNTER<10>.D 9.000
COUNTER<2>.Q COUNTER<1>.D 9.000
COUNTER<2>.Q COUNTER<4>.D 9.000
COUNTER<2>.Q COUNTER<5>.D 9.000
COUNTER<3>.Q COUNTER<0>.D 9.000
COUNTER<3>.Q COUNTER<10>.D 9.000
COUNTER<3>.Q COUNTER<1>.D 9.000
COUNTER<4>.Q COUNTER<0>.D 9.000
COUNTER<4>.Q COUNTER<10>.D 9.000
COUNTER<4>.Q COUNTER<1>.D 9.000
COUNTER<5>.Q COUNTER<0>.D 9.000
COUNTER<5>.Q COUNTER<10>.D 9.000
COUNTER<5>.Q COUNTER<1>.D 9.000
COUNTER<6>.Q COUNTER<0>.D 9.000
COUNTER<6>.Q COUNTER<10>.D 9.000
COUNTER<6>.Q COUNTER<1>.D 9.000
COUNTER<6>.Q COUNTER<6>.D 9.000
COUNTER<7>.Q COUNTER<0>.D 9.000
COUNTER<7>.Q COUNTER<10>.D 9.000
COUNTER<7>.Q COUNTER<1>.D 9.000
COUNTER<7>.Q COUNTER<6>.D 9.000
COUNTER<7>.Q COUNTER<7>.D 9.000
COUNTER<8>.Q COUNTER<0>.D 9.000
COUNTER<8>.Q COUNTER<10>.D 9.000
COUNTER<8>.Q COUNTER<1>.D 9.000
COUNTER<8>.Q COUNTER<6>.D 9.000
COUNTER<8>.Q COUNTER<7>.D 9.000
COUNTER<8>.Q COUNTER<8>.D 9.000
COUNTER<9>.Q COUNTER<0>.D 9.000
COUNTER<9>.Q COUNTER<10>.D 9.000
COUNTER<9>.Q COUNTER<1>.D 9.000
COUNTER<9>.Q COUNTER<6>.D 9.000
COUNTER<9>.Q COUNTER<9>.D 9.000

Clock to Setup for clock CLK
Source Destination Delay
CNT<0>.Q CLK_1M.D 9.000
CNT<0>.Q CNT<1>.D 9.000
CNT<0>.Q CNT<2>.D 9.000
CNT<0>.Q CNT<3>.D 9.000
CNT<1>.Q CLK_1M.D 9.000
CNT<1>.Q CNT<2>.D 9.000
CNT<1>.Q CNT<3>.D 9.000
CNT<2>.Q CLK_1M.D 9.000
CNT<2>.Q CNT<2>.D 9.000
CNT<2>.Q CNT<3>.D 9.000
CNT<3>.Q CLK_1M.D 9.000
CNT<3>.Q CNT<2>.D 9.000
CNT<3>.Q CNT<3>.D 9.000

Clock to Setup for clock WR
Source Destination Delay
DATA_REG<0>.Q DATA_REG<0>.D 9.000
DATA_REG<1>.Q DATA_REG<1>.D 9.000
DATA_REG<2>.Q DATA_REG<2>.D 9.000
DATA_REG<3>.Q DATA_REG<3>.D 9.000
DATA_REG<4>.Q DATA_REG<4>.D 9.000
DATA_REG<5>.Q DATA_REG<5>.D 9.000
DATA_REG<6>.Q DATA_REG<6>.D 9.000
DATA_REG<7>.Q DATA_REG<7>.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay
RD DATA_PORT<0> 10.000
RD DATA_PORT<1> 10.000
RD DATA_PORT<2> 10.000
RD DATA_PORT<3> 10.000
RD DATA_PORT<4> 10.000
RD DATA_PORT<5> 10.000
RD DATA_PORT<6> 10.000
RD DATA_PORT<7> 10.000



Number of paths analyzed: 273
Number of Timing errors: 273
Analysis Completed: Wed Apr 28 16:15:01 2010