********** Mapped Logic ********** |
$OpTx$$OpTx$FX_DC$51_INV$198 <= (COUNTER(10) AND COUNTER(11).LFBK); |
FTCPE_CLK_100: FTCPE port map (CLK_100,CLK_100_T,CLK,'0','0');
CLK_100_T <= (COUNTER(10) AND COUNTER(0) AND COUNTER(12) AND COUNTER(14) AND COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND NOT COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND NOT COUNTER(8).LFBK AND NOT COUNTER(9).LFBK AND NOT COUNTER(11).LFBK AND NOT COUNTER(13).LFBK AND NOT COUNTER(17).LFBK); |
FTCPE_COUNTER0: FTCPE port map (COUNTER(0),'1',CLK,'0','0'); |
FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER(0).LFBK,CLK,'0','0'); |
FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
COUNTER_T(2) <= (COUNTER(0) AND COUNTER(1)); |
FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
COUNTER_T(3) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2).LFBK); |
FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
COUNTER_T(4) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2).LFBK AND COUNTER(3).LFBK); |
FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
COUNTER_T(5) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK); |
FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
COUNTER_T(6) <= ((NOT COUNTER(0)) OR (NOT COUNTER(1)) OR (NOT COUNTER(2)) OR (NOT COUNTER(3)) OR (NOT COUNTER(4)) OR (SEG_2_OBUFE.EXP)); |
FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
COUNTER_T(7) <= ((COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(16).LFBK AND COUNTER(7).LFBK)); |
FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
COUNTER_T(8) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK); |
FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
COUNTER_T(9) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK); |
FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
COUNTER_T(10) <= ((COUNTER(9) AND COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(6).LFBK AND COUNTER(7).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND COUNTER(7).LFBK)); |
FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
COUNTER_T(11) <= (COUNTER(10) AND COUNTER(0) AND COUNTER(1) AND COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK); |
FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
COUNTER_T(12) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND COUNTER(7).LFBK)); |
FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
COUNTER_T(13) <= (COUNTER(10) AND COUNTER(0) AND COUNTER(12) AND COUNTER(1) AND COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(11).LFBK); |
FTCPE_COUNTER14: FTCPE port map (COUNTER(14),COUNTER_T(14),CLK,'0','0');
COUNTER_T(14) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND COUNTER(7).LFBK)); |
FTCPE_COUNTER15: FTCPE port map (COUNTER(15),COUNTER_T(15),CLK,'0','0');
COUNTER_T(15) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND COUNTER(7).LFBK)); |
FTCPE_COUNTER16: FTCPE port map (COUNTER(16),COUNTER_T(16),CLK,'0','0');
COUNTER_T(16) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND COUNTER(7).LFBK)); |
FTCPE_COUNTER17: FTCPE port map (COUNTER(17),COUNTER_T(17),CLK,'0','0');
COUNTER_T(17) <= (COUNTER(10) AND COUNTER(0) AND COUNTER(12) AND COUNTER(14) AND COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(11).LFBK AND COUNTER(13).LFBK); |
FTCPE_MIN_H0: FTCPE port map (MIN_H(0),MIN_H_T(0),CLK_100,NOT CLR,'0');
MIN_H_T(0) <= ((MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MIN_H(1).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK) OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND NOT MIN_H(2).LFBK) OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND MIN_H(0).LFBK)); |
FTCPE_MIN_H1: FTCPE port map (MIN_H(1),MIN_H_T(1),CLK_100,NOT CLR,'0');
MIN_H_T(1) <= ((MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MIN_H(1).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND MIN_H(0).LFBK) OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND NOT MIN_H(2).LFBK AND MIN_H(0).LFBK)); |
FTCPE_MIN_H2: FTCPE port map (MIN_H(2),MIN_H_T(2),CLK_100,NOT CLR,'0');
MIN_H_T(2) <= (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_H(1).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND NOT MIN_H(2).LFBK AND MIN_H(0).LFBK); |
FTCPE_MIN_L0: FTCPE port map (MIN_L(0),MIN_L_T(0),CLK_100,NOT CLR,'0');
MIN_L_T(0) <= (MSEC_L(0) AND SEC_H(0) AND NOT MSEC_H(1) AND NOT SEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK); |
FTCPE_MIN_L1: FTCPE port map (MIN_L(1),MIN_L_T(1),CLK_100,NOT CLR,'0');
MIN_L_T(1) <= ((MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND NOT MIN_L(3) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK) OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_L(1).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK) OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK)); |
FTCPE_MIN_L2: FTCPE port map (MIN_L(2),MIN_L_T(2),CLK_100,NOT CLR,'0');
MIN_L_T(2) <= (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_L(1).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK); |
FTCPE_MIN_L3: FTCPE port map (MIN_L(3),MIN_L_T(3),CLK_100,NOT CLR,'0');
MIN_L_T(3) <= ((MSEC_L(0) AND SEC_H(0) AND MIN_L(1) AND MIN_L(2) AND NOT MSEC_H(1) AND NOT SEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK AND MIN_L(0).LFBK) OR (MSEC_L(0) AND SEC_H(0) AND NOT MIN_L(1) AND NOT MIN_L(2) AND NOT MSEC_H(1) AND NOT SEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK AND MIN_L(0).LFBK AND MIN_L(3).LFBK)); |
FTCPE_MSEC_H0: FTCPE port map (MSEC_H(0),MSEC_H_T(0),CLK_100,NOT CLR,'0');
MSEC_H_T(0) <= (MSEC_L(0) AND NOT PAUSE AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK); |
FTCPE_MSEC_H1: FTCPE port map (MSEC_H(1),MSEC_H_T(1),CLK_100,NOT CLR,'0');
MSEC_H_T(1) <= ((MSEC_L(0) AND MSEC_H(0) AND MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_L(3) AND NOT PAUSE) OR (MSEC_L(0) AND MSEC_H(0) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND NOT MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE) OR (MSEC_L(0) AND MSEC_H(0) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_L(3) AND NOT PAUSE AND MSEC_H(1).LFBK)); |
FTCPE_MSEC_H2: FTCPE port map (MSEC_H(2),MSEC_H_T(2),CLK_100,NOT CLR,'0');
MSEC_H_T(2) <= (MSEC_L(0) AND MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK); |
FTCPE_MSEC_H3: FTCPE port map (MSEC_H(3),MSEC_H_T(3),CLK_100,NOT CLR,'0');
MSEC_H_T(3) <= ((MSEC_L(0) AND MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK) OR (MSEC_L(0) AND NOT MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK)); |
FTCPE_MSEC_L0: FTCPE port map (MSEC_L(0),PAUSE,CLK_100,NOT CLR,'0'); |
FTCPE_MSEC_L1: FTCPE port map (MSEC_L(1),MSEC_L_T(1),CLK_100,NOT CLR,'0');
MSEC_L_T(1) <= ((MSEC_L(0) AND NOT PAUSE AND MSEC_L(1).LFBK) OR (MSEC_L(0) AND NOT PAUSE AND MSEC_L(2).LFBK) OR (MSEC_L(0) AND NOT PAUSE AND NOT MSEC_L(3).LFBK)); |
FTCPE_MSEC_L2: FTCPE port map (MSEC_L(2),MSEC_L_T(2),CLK_100,NOT CLR,'0');
MSEC_L_T(2) <= (MSEC_L(0) AND NOT PAUSE AND MSEC_L(1).LFBK); |
FTCPE_MSEC_L3: FTCPE port map (MSEC_L(3),MSEC_L_T(3),CLK_100,NOT CLR,'0');
MSEC_L_T(3) <= ((MSEC_L(0) AND NOT PAUSE AND MSEC_L(1).LFBK AND MSEC_L(2).LFBK) OR (MSEC_L(0) AND NOT PAUSE AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK)); |
FTCPE_SEC_H0: FTCPE port map (SEC_H(0),SEC_H_T(0),CLK_100,NOT CLR,'0');
SEC_H_T(0) <= (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK); |
FTCPE_SEC_H1: FTCPE port map (SEC_H(1),SEC_H_T(1),CLK_100,NOT CLR,'0');
SEC_H_T(1) <= ((MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND NOT SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK) OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK) OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_H(3).LFBK AND SEC_L(3).LFBK)); |
FTCPE_SEC_H2: FTCPE port map (SEC_H(2),SEC_H_T(2),CLK_100,NOT CLR,'0');
SEC_H_T(2) <= ((MSEC_L(0) AND SEC_H(0) AND NOT MSEC_H(1) AND SEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK) OR (MSEC_L(0) AND SEC_H(0) AND NOT MSEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK)); |
FTCPE_SEC_H3: FTCPE port map (SEC_H(3),SEC_H_T(3),CLK_100,NOT CLR,'0');
SEC_H_T(3) <= (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK); |
FTCPE_SEC_L0: FTCPE port map (SEC_L(0),SEC_L_T(0),CLK_100,NOT CLR,'0');
SEC_L_T(0) <= (MSEC_L(0) AND NOT MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK); |
FTCPE_SEC_L1: FTCPE port map (SEC_L(1),SEC_L_T(1),CLK_100,NOT CLR,'0');
SEC_L_T(1) <= ((MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND SEC_L(1).LFBK) OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND SEC_L(2).LFBK) OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND NOT SEC_L(3).LFBK)); |
FTCPE_SEC_L2: FTCPE port map (SEC_L(2),SEC_L_T(2),CLK_100,NOT CLR,'0');
SEC_L_T(2) <= (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND SEC_L(1).LFBK); |
FTCPE_SEC_L3: FTCPE port map (SEC_L(3),SEC_L_T(3),CLK_100,NOT CLR,'0');
SEC_L_T(3) <= ((MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND SEC_L(1).LFBK AND SEC_L(2).LFBK) OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK)); |
SEG_I(0) <= NOT (((NOT SEG_BUF(1) AND SEG_BUF(2) AND NOT SEG_BUF(0) AND
NOT SEG_BUF(3)) OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND SEG_BUF(0) AND NOT SEG_BUF(3)))); SEG(0) <= SEG_I(0) when SEG_OE(0) = '1' else 'Z'; SEG_OE(0) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST.LFBK; |
SEG_I(1) <= NOT (((SEG_BUF(1) AND SEG_BUF(2) AND NOT SEG_BUF(0) AND
NOT SEG_BUF(3)) OR (NOT SEG_BUF(1) AND SEG_BUF(2) AND SEG_BUF(0) AND NOT SEG_BUF(3)))); SEG(1) <= SEG_I(1) when SEG_OE(1) = '1' else 'Z'; SEG_OE(1) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST.LFBK; |
SEG_I(2) <= NOT ((SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(0) AND
NOT SEG_BUF(3))); SEG(2) <= SEG_I(2) when SEG_OE(2) = '1' else 'Z'; SEG_OE(2) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST; |
SEG_I(3) <= NOT (((SEG_BUF(1) AND SEG_BUF(2) AND SEG_BUF(0) AND
NOT SEG_BUF(3)) OR (NOT SEG_BUF(1) AND SEG_BUF(2) AND NOT SEG_BUF(0) AND NOT SEG_BUF(3)) OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND SEG_BUF(0) AND NOT SEG_BUF(3)))); SEG(3) <= SEG_I(3) when SEG_OE(3) = '1' else 'Z'; SEG_OE(3) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST; |
SEG_I(4) <= ((SEG_BUF(1) AND NOT SEG_BUF(0) AND NOT SEG_BUF(3))
OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(0))); SEG(4) <= SEG_I(4) when SEG_OE(4) = '1' else 'Z'; SEG_OE(4) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST; |
SEG_I(5) <= NOT (((SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(3))
OR (SEG_BUF(1) AND SEG_BUF(0) AND NOT SEG_BUF(3)) OR (NOT SEG_BUF(2) AND SEG_BUF(0) AND NOT SEG_BUF(3)))); SEG(5) <= SEG_I(5) when SEG_OE(5) = '1' else 'Z'; SEG_OE(5) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST; |
SEG_I(6) <= NOT (((NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(3))
OR (SEG_BUF(1) AND SEG_BUF(2) AND SEG_BUF(0) AND NOT SEG_BUF(3)))); SEG(6) <= SEG_I(6) when SEG_OE(6) = '1' else 'Z'; SEG_OE(6) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST; |
SEG_I(7) <= '0';
SEG(7) <= SEG_I(7) when SEG_OE(7) = '1' else 'Z'; SEG_OE(7) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST; |
SEG_6_OBUFE/SEG_6_OBUFE_TRST <= ((NOT SEG_BUF(3))
OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2))); |
SEG_BUF(0)/SEG_BUF(0)_RSTF <= ((EXP0_.EXP)
OR (NOT MSEC_L(0) AND NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10)) OR (NOT SEC_H(0) AND COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10)) OR (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND NOT MSEC_H(0).LFBK) OR (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10) AND NOT MIN_L(0).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10) AND NOT SEC_L(0).LFBK)); |
FDCPE_SEG_BUF0: FDCPE port map (SEG_BUF(0),'0','0',SEG_BUF(0)/SEG_BUF(0)_RSTF,SEG_BUF_PRE(0));
SEG_BUF_PRE(0) <= (NOT $OpTx$$OpTx$FX_DC$51_INV$198 AND NOT SEG_BUF(0)/SEG_BUF(0)_RSTF); |
FDCPE_SEG_BUF1: FDCPE port map (SEG_BUF(1),'0','0',SEG_BUF(1)/SEG_BUF(1)_RSTF,SEG_BUF_PRE(1));
SEG_BUF_PRE(1) <= (NOT SEG_BUF(1)/SEG_BUF(1)_RSTF AND NOT $OpTx$$OpTx$FX_DC$51_INV$198); |
SEG_BUF(1)/SEG_BUF(1)_RSTF <= ((SEL_2.EXP)
OR (NOT MSEC_L(1) AND NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10)) OR (COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10) AND NOT SEC_H(1).LFBK) OR (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND NOT MSEC_H(1).LFBK) OR (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10) AND NOT MIN_L(1).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10) AND NOT SEC_L(1).LFBK)); |
FDCPE_SEG_BUF2: FDCPE port map (SEG_BUF(2),'0','0',SEG_BUF(2)/SEG_BUF(2)_RSTF,SEG_BUF_PRE(2));
SEG_BUF_PRE(2) <= (NOT $OpTx$$OpTx$FX_DC$51_INV$198 AND NOT SEG_BUF(2)/SEG_BUF(2)_RSTF); |
SEG_BUF(2)/SEG_BUF(2)_RSTF <= ((SEL_1/SEL_1_RSTF__$INT.EXP)
OR (NOT MIN_L(2) AND NOT COUNTER(10) AND NOT COUNTER(9).LFBK AND COUNTER(11).LFBK) OR (NOT MSEC_H(2) AND NOT COUNTER(10) AND COUNTER(9).LFBK AND NOT COUNTER(11).LFBK) OR (NOT MSEC_L(2) AND NOT COUNTER(10) AND NOT COUNTER(9).LFBK AND NOT COUNTER(11).LFBK) OR (NOT SEC_H(2) AND COUNTER(10) AND COUNTER(9).LFBK AND NOT COUNTER(11).LFBK) OR (NOT SEC_L(2) AND COUNTER(10) AND NOT COUNTER(9).LFBK AND NOT COUNTER(11).LFBK)); |
FDCPE_SEG_BUF3: FDCPE port map (SEG_BUF(3),'0','0',SEG_BUF_CLR(3),SEG_BUF(3)/SEG_BUF(3)_SETF);
SEG_BUF_CLR(3) <= (NOT $OpTx$$OpTx$FX_DC$51_INV$198 AND NOT SEG_BUF(3)/SEG_BUF(3)_SETF); |
SEG_BUF(3)/SEG_BUF(3)_SETF <= ((SEC_H(3) AND COUNTER(9) AND NOT COUNTER(11) AND
COUNTER(10)) OR (SEC_L(3) AND NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10)) OR (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND MSEC_H(3).LFBK) OR (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10) AND MIN_L(3).LFBK) OR (NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND MSEC_L(3).LFBK)); |
FDCPE_SEL0: FDCPE port map (SEL(0),'0','0',NOT SEL_0/SEL_0_RSTF__$INT,SEL_PRE(0));
SEL_PRE(0) <= (NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10)); |
FDCPE_SEL1: FDCPE port map (SEL(1),'0','0',NOT SEL_1/SEL_1_RSTF__$INT,SEL_PRE(1));
SEL_PRE(1) <= (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10)); |
FDCPE_SEL2: FDCPE port map (SEL(2),'0','0',NOT SEL_2/SEL_2_RSTF__$INT,SEL_PRE(2));
SEL_PRE(2) <= (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10)); |
FDCPE_SEL3: FDCPE port map (SEL(3),'0','0',NOT SEL_3/SEL_3_RSTF__$INT,SEL_PRE(3));
SEL_PRE(3) <= (COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10).LFBK); |
FDCPE_SEL4: FDCPE port map (SEL(4),'0','0',NOT SEL_4/SEL_4_RSTF__$INT,SEL_PRE(4));
SEL_PRE(4) <= (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10).LFBK); |
FDCPE_SEL5: FDCPE port map (SEL(5),'0','0',NOT SEL_5/SEL_5_RSTF__$INT,SEL_PRE(5));
SEL_PRE(5) <= (COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10).LFBK); |
SEL_0/SEL_0_RSTF__$INT <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(10))
OR (NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10))); |
SEL_1/SEL_1_RSTF__$INT <= ((COUNTER(10) AND COUNTER(9).LFBK AND COUNTER(11).LFBK)
OR (NOT COUNTER(10) AND COUNTER(9).LFBK AND NOT COUNTER(11).LFBK)); |
SEL_2/SEL_2_RSTF__$INT <= ((COUNTER(10) AND COUNTER(9).LFBK AND COUNTER(11).LFBK)
OR (COUNTER(10) AND NOT COUNTER(9).LFBK AND NOT COUNTER(11).LFBK)); |
SEL_3/SEL_3_RSTF__$INT <= (COUNTER(10) AND COUNTER(9).LFBK); |
SEL_4/SEL_4_RSTF__$INT <= ((COUNTER(10) AND COUNTER(9).LFBK AND COUNTER(11).LFBK)
OR (NOT COUNTER(10) AND NOT COUNTER(9).LFBK AND COUNTER(11).LFBK)); |
SEL_5/SEL_5_RSTF__$INT <= (COUNTER(9) AND COUNTER(11)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |