cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: STOPWATCH                           Date:  4-23-2010,  8:21PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
72 /108 ( 67%) 173 /540  ( 32%) 122/216 ( 56%)   52 /108 ( 48%) 17 /69  ( 25%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          16/18       24/36       24          24/90       0/12
FB2          16/18       31/36       31          47/90       2/12
FB3           8/18       10/36       10          12/90       0/12
FB4          16/18       26/36       26          42/90       9/11
FB5           0/18        0/36        0           0/90       0/11
FB6          16/18       31/36       31          48/90       3/11
             -----       -----                   -----       -----     
             72/108     122/216                 173/540     14/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
Global output enable net(s) unused.
The complement of 'CLR' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    1           1    |  I/O              :    15      63
Output        :   14          14    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     17          17

** Power Data **

There are 72 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 14 Outputs **

Signal                        Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                          Pts   Inps          No.  Type    Use     Mode Rate State
SEG<1>                        3     5     FB2_2   71   I/O     O       STD  FAST 
SEG<0>                        3     5     FB2_3   72   I/O     O       STD  FAST 
SEL<3>                        2     4     FB4_2   57   I/O     O       STD  FAST RESET
SEL<4>                        2     4     FB4_3   58   I/O     O       STD  FAST RESET
SEL<5>                        2     4     FB4_5   61   I/O     O       STD  FAST RESET
SEG<7>                        1     1     FB4_9   65   I/O     O       STD  FAST 
SEG<6>                        3     5     FB4_11  66   I/O     O       STD  FAST 
SEG<5>                        4     5     FB4_12  67   I/O     O       STD  FAST 
SEG<4>                        3     5     FB4_14  68   I/O     O       STD  FAST 
SEG<3>                        4     5     FB4_15  69   I/O     O       STD  FAST 
SEG<2>                        2     5     FB4_17  70   I/O     O       STD  FAST 
SEL<0>                        2     4     FB6_14  54   I/O     O       STD  FAST RESET
SEL<1>                        2     4     FB6_15  55   I/O     O       STD  FAST RESET
SEL<2>                        2     4     FB6_17  56   I/O     O       STD  FAST RESET

** 58 Buried Nodes **

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
SEL_3/SEL_3_RSTF__$INT        1     2     FB1_3   STD  
COUNTER<9>                    1     9     FB1_4   STD  RESET
COUNTER<8>                    1     8     FB1_5   STD  RESET
COUNTER<5>                    1     5     FB1_6   STD  RESET
COUNTER<4>                    1     4     FB1_7   STD  RESET
COUNTER<3>                    1     3     FB1_8   STD  RESET
COUNTER<2>                    1     2     FB1_9   STD  RESET
COUNTER<17>                   1     17    FB1_10  STD  RESET
COUNTER<13>                   1     13    FB1_11  STD  RESET
COUNTER<11>                   1     11    FB1_12  STD  RESET
CLK_100                       1     18    FB1_13  STD  RESET
$OpTx$$OpTx$FX_DC$51_INV$198  1     2     FB1_14  STD  
SEL_4/SEL_4_RSTF__$INT        2     3     FB1_15  STD  
SEL_2/SEL_2_RSTF__$INT        2     3     FB1_16  STD  
SEL_1/SEL_1_RSTF__$INT        2     3     FB1_17  STD  
SEG_BUF<2>/SEG_BUF<2>_RSTF    6     9     FB1_18  STD  
SEL_0/SEL_0_RSTF__$INT        2     3     FB2_5   STD  
SEG_6_OBUFE/SEG_6_OBUFE_TRST  2     3     FB2_6   STD  
SEC_L<0>                      2     10    FB2_7   STD  RESET
MSEC_L<2>                     2     4     FB2_8   STD  RESET
MSEC_H<2>                     2     8     FB2_9   STD  RESET
MSEC_H<0>                     2     6     FB2_10  STD  RESET
MIN_L<0>                      2     18    FB2_11  STD  RESET
SEC_H<2>                      3     18    FB2_12  STD  RESET
MSEC_L<3>                     3     6     FB2_13  STD  RESET
MSEC_H<3>                     3     10    FB2_14  STD  RESET
MIN_L<3>                      3     22    FB2_15  STD  RESET
MSEC_L<1>                     4     6     FB2_16  STD  RESET
SEG_BUF<3>/SEG_BUF<3>_SETF    5     8     FB2_17  STD  
SEG_BUF<0>/SEG_BUF<0>_RSTF    6     9     FB2_18  STD  
SEL_5/SEL_5_RSTF__$INT        1     2     FB3_11  STD  
COUNTER<1>                    1     1     FB3_12  STD  RESET
COUNTER<0>                    0     0     FB3_13  STD  RESET
MSEC_L<0>                     2     2     FB3_14  STD  RESET
SEG_BUF<3>                    2     2     FB3_15  STD  RESET
SEG_BUF<2>                    2     2     FB3_16  STD  RESET
SEG_BUF<1>                    2     2     FB3_17  STD  RESET
SEG_BUF<0>                    2     2     FB3_18  STD  RESET
COUNTER<7>                    2     18    FB4_6   STD  RESET
COUNTER<16>                   2     18    FB4_7   STD  RESET

Signal                        Total Total Loc     Pwr  Reg Init
Name                          Pts   Inps          Mode State
COUNTER<15>                   2     18    FB4_8   STD  RESET
COUNTER<14>                   2     18    FB4_10  STD  RESET
COUNTER<12>                   2     18    FB4_13  STD  RESET
COUNTER<10>                   2     18    FB4_16  STD  RESET
COUNTER<6>                    7     18    FB4_18  STD  RESET
SEC_L<2>                      2     12    FB6_3   STD  RESET
SEC_H<3>                      2     17    FB6_4   STD  RESET
SEC_H<0>                      2     14    FB6_5   STD  RESET
MIN_L<2>                      2     20    FB6_6   STD  RESET
MIN_H<2>                      2     25    FB6_7   STD  RESET
SEC_L<3>                      3     14    FB6_8   STD  RESET
MIN_H<1>                      3     25    FB6_9   STD  RESET
SEC_L<1>                      4     14    FB6_10  STD  RESET
SEC_H<1>                      4     18    FB6_11  STD  RESET
MSEC_H<1>                     4     10    FB6_12  STD  RESET
MIN_L<1>                      4     22    FB6_13  STD  RESET
MIN_H<0>                      4     25    FB6_16  STD  RESET
SEG_BUF<1>/SEG_BUF<1>_RSTF    6     9     FB6_18  STD  

** 3 Inputs **

Signal                        Loc     Pin  Pin     Pin     
Name                                  No.  Type    Use     
CLK                           FB1_12  9    GCK/I/O GCK
CLR                           FB2_5   74   GSR/I/O GSR
PAUSE                         FB5_8   36   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               24/12
Number of signals used by logic mapping into function block:  24
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     
SEL_3/SEL_3_RSTF__$INT
                      1       0     0   4     FB1_3   2     I/O     (b)
COUNTER<9>            1       0     0   4     FB1_4         (b)     (b)
COUNTER<8>            1       0     0   4     FB1_5   3     I/O     (b)
COUNTER<5>            1       0     0   4     FB1_6   4     I/O     (b)
COUNTER<4>            1       0     0   4     FB1_7         (b)     (b)
COUNTER<3>            1       0     0   4     FB1_8   5     I/O     (b)
COUNTER<2>            1       0     0   4     FB1_9   6     I/O     (b)
COUNTER<17>           1       0     0   4     FB1_10        (b)     (b)
COUNTER<13>           1       0     0   4     FB1_11  7     I/O     (b)
COUNTER<11>           1       0     0   4     FB1_12  9     GCK/I/O GCK
CLK_100               1       0     0   4     FB1_13        (b)     (b)
$OpTx$$OpTx$FX_DC$51_INV$198
                      1       0     0   4     FB1_14  10    GCK/I/O (b)
SEL_4/SEL_4_RSTF__$INT
                      2       0     0   3     FB1_15  11    I/O     (b)
SEL_2/SEL_2_RSTF__$INT
                      2       0     0   3     FB1_16  12    GCK/I/O (b)
SEL_1/SEL_1_RSTF__$INT
                      2       0   \/1   2     FB1_17  13    I/O     (b)
SEG_BUF<2>/SEG_BUF<2>_RSTF
                      6       1<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: COUNTER<0>         9: COUNTER<17>.LFBK  17: COUNTER<8>.LFBK 
  2: COUNTER<10>       10: COUNTER<1>        18: COUNTER<9>.LFBK 
  3: COUNTER<11>.LFBK  11: COUNTER<2>.LFBK   19: MIN_H<2> 
  4: COUNTER<12>       12: COUNTER<3>.LFBK   20: MIN_L<2> 
  5: COUNTER<13>.LFBK  13: COUNTER<4>.LFBK   21: MSEC_H<2> 
  6: COUNTER<14>       14: COUNTER<5>.LFBK   22: MSEC_L<2> 
  7: COUNTER<15>       15: COUNTER<6>        23: SEC_H<2> 
  8: COUNTER<16>       16: COUNTER<7>        24: SEC_L<2> 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEL_3/SEL_3_RSTF__$INT 
                     .X...............X...................... 2       2
COUNTER<9>           X........XXXXXXXX....................... 9       9
COUNTER<8>           X........XXXXXXX........................ 8       8
COUNTER<5>           X........XXXX........................... 5       5
COUNTER<4>           X........XXX............................ 4       4
COUNTER<3>           X........XX............................. 3       3
COUNTER<2>           X........X.............................. 2       2
COUNTER<17>          XXXXXXXX.XXXXXXXXX...................... 17      17
COUNTER<13>          XXXX.....XXXXXXXXX...................... 13      13
COUNTER<11>          XX.......XXXXXXXXX...................... 11      11
CLK_100              XXXXXXXXXXXXXXXXXX...................... 18      18
$OpTx$$OpTx$FX_DC$51_INV$198 
                     .XX..................................... 2       2
SEL_4/SEL_4_RSTF__$INT 
                     .XX..............X...................... 3       3
SEL_2/SEL_2_RSTF__$INT 
                     .XX..............X...................... 3       3
SEL_1/SEL_1_RSTF__$INT 
                     .XX..............X...................... 3       3
SEG_BUF<2>/SEG_BUF<2>_RSTF 
                     .XX..............XXXXXXX................ 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB2_1         (b)     (b)
SEG<1>                3       0     0   2     FB2_2   71    I/O     O
SEG<0>                3       0     0   2     FB2_3   72    I/O     O
(unused)              0       0     0   5     FB2_4         (b)     
SEL_0/SEL_0_RSTF__$INT
                      2       0     0   3     FB2_5   74    GSR/I/O GSR
SEG_6_OBUFE/SEG_6_OBUFE_TRST
                      2       0     0   3     FB2_6   75    I/O     (b)
SEC_L<0>              2       0     0   3     FB2_7         (b)     (b)
MSEC_L<2>             2       0     0   3     FB2_8   76    GTS/I/O (b)
MSEC_H<2>             2       0     0   3     FB2_9   77    GTS/I/O (b)
MSEC_H<0>             2       0     0   3     FB2_10        (b)     (b)
MIN_L<0>              2       0     0   3     FB2_11  79    I/O     (b)
SEC_H<2>              3       0     0   2     FB2_12  80    I/O     (b)
MSEC_L<3>             3       0     0   2     FB2_13        (b)     (b)
MSEC_H<3>             3       0     0   2     FB2_14  81    I/O     (b)
MIN_L<3>              3       0     0   2     FB2_15  82    I/O     (b)
MSEC_L<1>             4       0     0   1     FB2_16  83    I/O     (b)
SEG_BUF<3>/SEG_BUF<3>_SETF
                      5       0     0   0     FB2_17  84    I/O     (b)
SEG_BUF<0>/SEG_BUF<0>_RSTF
                      6       1<-   0   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK_100           12: MSEC_H<2>.LFBK    22: SEC_H<3> 
  2: COUNTER<10>       13: MSEC_H<3>.LFBK    23: SEC_L<0>.LFBK 
  3: COUNTER<11>       14: MSEC_L<0>         24: SEC_L<1> 
  4: COUNTER<9>        15: MSEC_L<1>.LFBK    25: SEC_L<2> 
  5: MIN_H<0>          16: MSEC_L<2>.LFBK    26: SEC_L<3> 
  6: MIN_L<0>.LFBK     17: MSEC_L<3>.LFBK    27: SEG_6_OBUFE/SEG_6_OBUFE_TRST.LFBK 
  7: MIN_L<1>          18: PAUSE             28: SEG_BUF<0> 
  8: MIN_L<2>          19: SEC_H<0>          29: SEG_BUF<1> 
  9: MIN_L<3>.LFBK     20: SEC_H<1>          30: SEG_BUF<2> 
 10: MSEC_H<0>.LFBK    21: SEC_H<2>.LFBK     31: SEG_BUF<3> 
 11: MSEC_H<1>        

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEG<1>               ..........................XXXXX......... 5       5
SEG<0>               ..........................XXXXX......... 5       5
SEL_0/SEL_0_RSTF__$INT 
                     .XXX.................................... 3       3
SEG_6_OBUFE/SEG_6_OBUFE_TRST 
                     ............................XXX......... 3       3
SEC_L<0>             X........XXXXXXXXX...................... 10      10
MSEC_L<2>            X............XX..X...................... 4       4
MSEC_H<2>            X........XX..XXXXX...................... 8       8
MSEC_H<0>            X............XXXXX...................... 6       6
MIN_L<0>             X........XXXXXXXXXXXXXXXXX.............. 18      18
SEC_H<2>             X........XXXXXXXXXXXXXXXXX.............. 18      18
MSEC_L<3>            X............XXXXX...................... 6       6
MSEC_H<3>            X........XXXXXXXXX...................... 10      10
MIN_L<3>             X....XXXXXXXXXXXXXXXXXXXXX.............. 22      22
MSEC_L<1>            X............XXXXX...................... 6       6
SEG_BUF<3>/SEG_BUF<3>_SETF 
                     .XXX....X...X...X....X...X.............. 8       8
SEG_BUF<0>/SEG_BUF<0>_RSTF 
                     .XXXXX...X...X....X...X................. 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               10/26
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   14    I/O     
(unused)              0       0     0   5     FB3_3   15    I/O     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   17    I/O     
(unused)              0       0     0   5     FB3_6   18    I/O     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   19    I/O     
(unused)              0       0     0   5     FB3_9   20    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
SEL_5/SEL_5_RSTF__$INT
                      1       0     0   4     FB3_11  21    I/O     (b)
COUNTER<1>            1       0     0   4     FB3_12  23    I/O     (b)
COUNTER<0>            0       0     0   5     FB3_13        (b)     (b)
MSEC_L<0>             2       0     0   3     FB3_14  24    I/O     (b)
SEG_BUF<3>            2       0     0   3     FB3_15  25    I/O     (b)
SEG_BUF<2>            2       0     0   3     FB3_16  26    I/O     (b)
SEG_BUF<1>            2       0     0   3     FB3_17  31    I/O     (b)
SEG_BUF<0>            2       0     0   3     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$51_INV$198   5: COUNTER<9>                   8: SEG_BUF<1>/SEG_BUF<1>_RSTF 
  2: CLK_100                        6: PAUSE                        9: SEG_BUF<2>/SEG_BUF<2>_RSTF 
  3: COUNTER<0>.LFBK                7: SEG_BUF<0>/SEG_BUF<0>_RSTF  10: SEG_BUF<3>/SEG_BUF<3>_SETF 
  4: COUNTER<11>                  

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEL_5/SEL_5_RSTF__$INT 
                     ...XX................................... 2       2
COUNTER<1>           ..X..................................... 1       1
COUNTER<0>           ........................................ 0       0
MSEC_L<0>            .X...X.................................. 2       2
SEG_BUF<3>           X........X.............................. 2       2
SEG_BUF<2>           X.......X............................... 2       2
SEG_BUF<1>           X......X................................ 2       2
SEG_BUF<0>           X.....X................................. 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               26/10
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
SEL<3>                2       0     0   3     FB4_2   57    I/O     O
SEL<4>                2       0     0   3     FB4_3   58    I/O     O
(unused)              0       0     0   5     FB4_4         (b)     
SEL<5>                2       0     0   3     FB4_5   61    I/O     O
COUNTER<7>            2       0     0   3     FB4_6   62    I/O     (b)
COUNTER<16>           2       0     0   3     FB4_7         (b)     (b)
COUNTER<15>           2       0     0   3     FB4_8   63    I/O     (b)
SEG<7>                1       0     0   4     FB4_9   65    I/O     O
COUNTER<14>           2       0     0   3     FB4_10        (b)     (b)
SEG<6>                3       0     0   2     FB4_11  66    I/O     O
SEG<5>                4       0     0   1     FB4_12  67    I/O     O
COUNTER<12>           2       0     0   3     FB4_13        (b)     (b)
SEG<4>                3       0     0   2     FB4_14  68    I/O     O
SEG<3>                4       0     0   1     FB4_15  69    I/O     O
COUNTER<10>           2       0     0   3     FB4_16        (b)     (b)
SEG<2>                2       0   \/2   1     FB4_17  70    I/O     O
COUNTER<6>            7       2<-   0   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: COUNTER<0>        10: COUNTER<1>        19: SEG_6_OBUFE/SEG_6_OBUFE_TRST 
  2: COUNTER<10>.LFBK  11: COUNTER<2>        20: SEG_BUF<0> 
  3: COUNTER<11>       12: COUNTER<3>        21: SEG_BUF<1> 
  4: COUNTER<12>.LFBK  13: COUNTER<4>        22: SEG_BUF<2> 
  5: COUNTER<13>       14: COUNTER<5>        23: SEG_BUF<3> 
  6: COUNTER<14>.LFBK  15: COUNTER<6>.LFBK   24: SEL_3/SEL_3_RSTF__$INT 
  7: COUNTER<15>.LFBK  16: COUNTER<7>.LFBK   25: SEL_4/SEL_4_RSTF__$INT 
  8: COUNTER<16>.LFBK  17: COUNTER<8>        26: SEL_5/SEL_5_RSTF__$INT 
  9: COUNTER<17>       18: COUNTER<9>       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEL<3>               .XX..............X.....X................ 4       4
SEL<4>               .XX..............X......X............... 4       4
SEL<5>               .XX..............X.......X.............. 4       4
COUNTER<7>           XXXXXXXXXXXXXXXXXX...................... 18      18
COUNTER<16>          XXXXXXXXXXXXXXXXXX...................... 18      18
COUNTER<15>          XXXXXXXXXXXXXXXXXX...................... 18      18
SEG<7>               ..................X..................... 1       1
COUNTER<14>          XXXXXXXXXXXXXXXXXX...................... 18      18
SEG<6>               ..................XXXXX................. 5       5
SEG<5>               ..................XXXXX................. 5       5
COUNTER<12>          XXXXXXXXXXXXXXXXXX...................... 18      18
SEG<4>               ..................XXXXX................. 5       5
SEG<3>               ..................XXXXX................. 5       5
COUNTER<10>          XXXXXXXXXXXXXXXXXX...................... 18      18
SEG<2>               ..................XXXXX................. 5       5
COUNTER<6>           XXXXXXXXXXXXXXXXXX...................... 18      18
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   32    I/O     
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     I
(unused)              0       0     0   5     FB5_9   37    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
(unused)              0       0     0   5     FB6_2   45    I/O     
SEC_L<2>              2       0     0   3     FB6_3   46    I/O     (b)
SEC_H<3>              2       0     0   3     FB6_4         (b)     (b)
SEC_H<0>              2       0     0   3     FB6_5   47    I/O     (b)
MIN_L<2>              2       0     0   3     FB6_6   48    I/O     (b)
MIN_H<2>              2       0     0   3     FB6_7         (b)     (b)
SEC_L<3>              3       0     0   2     FB6_8   50    I/O     (b)
MIN_H<1>              3       0     0   2     FB6_9   51    I/O     (b)
SEC_L<1>              4       0     0   1     FB6_10        (b)     (b)
SEC_H<1>              4       0     0   1     FB6_11  52    I/O     (b)
MSEC_H<1>             4       0     0   1     FB6_12  53    I/O     (b)
MIN_L<1>              4       0     0   1     FB6_13        (b)     (b)
SEL<0>                2       0     0   3     FB6_14  54    I/O     O
SEL<1>                2       0     0   3     FB6_15  55    I/O     O
MIN_H<0>              4       0     0   1     FB6_16        (b)     (b)
SEL<2>                2       0   \/1   2     FB6_17  56    I/O     O
SEG_BUF<1>/SEG_BUF<1>_RSTF
                      6       1<-   0   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK_100           12: MSEC_H<0>         22: SEC_H<1>.LFBK 
  2: COUNTER<10>       13: MSEC_H<1>.LFBK    23: SEC_H<2> 
  3: COUNTER<11>       14: MSEC_H<2>         24: SEC_H<3>.LFBK 
  4: COUNTER<9>        15: MSEC_H<3>         25: SEC_L<0> 
  5: MIN_H<0>.LFBK     16: MSEC_L<0>         26: SEC_L<1>.LFBK 
  6: MIN_H<1>.LFBK     17: MSEC_L<1>         27: SEC_L<2>.LFBK 
  7: MIN_H<2>.LFBK     18: MSEC_L<2>         28: SEC_L<3>.LFBK 
  8: MIN_L<0>          19: MSEC_L<3>         29: SEL_0/SEL_0_RSTF__$INT 
  9: MIN_L<1>.LFBK     20: PAUSE             30: SEL_1/SEL_1_RSTF__$INT 
 10: MIN_L<2>.LFBK     21: SEC_H<0>.LFBK     31: SEL_2/SEL_2_RSTF__$INT 
 11: MIN_L<3>         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEC_L<2>             X..........XXXXXXXXX....XX.............. 12      12
SEC_H<3>             X..........XXXXXXXXXXXX.XXXX............ 17      17
SEC_H<0>             X..........XXXXXXXXX....XXXX............ 14      14
MIN_L<2>             X......XX..XXXXXXXXXXXXXXXXX............ 20      20
MIN_H<2>             X...XXXXXXXXXXXXXXXXXXXXXXXX............ 25      25
SEC_L<3>             X..........XXXXXXXXX....XXXX............ 14      14
MIN_H<1>             X...XXXXXXXXXXXXXXXXXXXXXXXX............ 25      25
SEC_L<1>             X..........XXXXXXXXX....XXXX............ 14      14
SEC_H<1>             X..........XXXXXXXXXXXXXXXXX............ 18      18
MSEC_H<1>            X..........XXXXXXXXX.................... 10      10
MIN_L<1>             X......XXXXXXXXXXXXXXXXXXXXX............ 22      22
SEL<0>               .XXX........................X........... 4       4
SEL<1>               .XXX.........................X.......... 4       4
MIN_H<0>             X...XXXXXXXXXXXXXXXXXXXXXXXX............ 25      25
SEL<2>               .XXX..........................X......... 4       4
SEG_BUF<1>/SEG_BUF<1>_RSTF 
                     .XXX.X..X...X...X....X...X.............. 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$$OpTx$FX_DC$51_INV$198 <= (COUNTER(10) AND COUNTER(11).LFBK);

FTCPE_CLK_100: FTCPE port map (CLK_100,CLK_100_T,CLK,'0','0');
CLK_100_T <= (COUNTER(10) AND COUNTER(0) AND COUNTER(12) AND 
	COUNTER(14) AND COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND 
	NOT COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND NOT COUNTER(8).LFBK AND 
	NOT COUNTER(9).LFBK AND NOT COUNTER(11).LFBK AND NOT COUNTER(13).LFBK AND 
	NOT COUNTER(17).LFBK);

FTCPE_COUNTER0: FTCPE port map (COUNTER(0),'1',CLK,'0','0');

FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER(0).LFBK,CLK,'0','0');

FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
COUNTER_T(2) <= (COUNTER(0) AND COUNTER(1));

FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
COUNTER_T(3) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2).LFBK);

FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
COUNTER_T(4) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2).LFBK AND 
	COUNTER(3).LFBK);

FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
COUNTER_T(5) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(2).LFBK AND 
	COUNTER(3).LFBK AND COUNTER(4).LFBK);

FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
COUNTER_T(6) <= ((NOT COUNTER(0))
	OR (NOT COUNTER(1))
	OR (NOT COUNTER(2))
	OR (NOT COUNTER(3))
	OR (NOT COUNTER(4))
	OR (SEG_2_OBUFE.EXP));

FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
COUNTER_T(7) <= ((COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND 
	NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND 
	COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK AND COUNTER(16).LFBK AND COUNTER(7).LFBK));

FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
COUNTER_T(8) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK);

FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
COUNTER_T(9) <= (COUNTER(0) AND COUNTER(1) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK);

FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
COUNTER_T(10) <= ((COUNTER(9) AND COUNTER(0) AND COUNTER(1) AND 
	COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND 
	COUNTER(8) AND COUNTER(6).LFBK AND COUNTER(7).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND 
	NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND 
	COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND 
	COUNTER(7).LFBK));

FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
COUNTER_T(11) <= (COUNTER(10) AND COUNTER(0) AND COUNTER(1) AND 
	COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK);

FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
COUNTER_T(12) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND 
	COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND 
	COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND 
	NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND 
	COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND 
	COUNTER(7).LFBK));

FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
COUNTER_T(13) <= (COUNTER(10) AND COUNTER(0) AND COUNTER(12) AND 
	COUNTER(1) AND COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND 
	COUNTER(3).LFBK AND COUNTER(4).LFBK AND COUNTER(5).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(9).LFBK AND COUNTER(11).LFBK);

FTCPE_COUNTER14: FTCPE port map (COUNTER(14),COUNTER_T(14),CLK,'0','0');
COUNTER_T(14) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND 
	COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND 
	NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND 
	COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND 
	COUNTER(7).LFBK));

FTCPE_COUNTER15: FTCPE port map (COUNTER(15),COUNTER_T(15),CLK,'0','0');
COUNTER_T(15) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND 
	COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND 
	NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND 
	COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND 
	COUNTER(7).LFBK));

FTCPE_COUNTER16: FTCPE port map (COUNTER(16),COUNTER_T(16),CLK,'0','0');
COUNTER_T(16) <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(0) AND 
	COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND COUNTER(8) AND COUNTER(10).LFBK AND 
	COUNTER(12).LFBK AND COUNTER(14).LFBK AND COUNTER(15).LFBK AND 
	COUNTER(6).LFBK AND COUNTER(7).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(0) AND 
	NOT COUNTER(13) AND COUNTER(1) AND COUNTER(2) AND COUNTER(3) AND 
	COUNTER(4) AND COUNTER(5) AND NOT COUNTER(8) AND NOT COUNTER(17) AND 
	COUNTER(10).LFBK AND COUNTER(12).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK AND COUNTER(16).LFBK AND NOT COUNTER(6).LFBK AND 
	COUNTER(7).LFBK));

FTCPE_COUNTER17: FTCPE port map (COUNTER(17),COUNTER_T(17),CLK,'0','0');
COUNTER_T(17) <= (COUNTER(10) AND COUNTER(0) AND COUNTER(12) AND 
	COUNTER(14) AND COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND 
	COUNTER(6) AND COUNTER(7) AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(8).LFBK AND 
	COUNTER(9).LFBK AND COUNTER(11).LFBK AND COUNTER(13).LFBK);



FTCPE_MIN_H0: FTCPE port map (MIN_H(0),MIN_H_T(0),CLK_100,NOT CLR,'0');
MIN_H_T(0) <= ((MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	NOT MIN_H(1).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND 
	NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND 
	SEC_L(3).LFBK)
	OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND 
	NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND 
	NOT MIN_H(2).LFBK)
	OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND 
	NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND 
	MIN_H(0).LFBK));

FTCPE_MIN_H1: FTCPE port map (MIN_H(1),MIN_H_T(1),CLK_100,NOT CLR,'0');
MIN_H_T(1) <= ((MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	NOT MIN_H(1).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND 
	NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND 
	SEC_L(3).LFBK AND MIN_H(0).LFBK)
	OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND 
	NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND SEC_L(3).LFBK AND 
	NOT MIN_H(2).LFBK AND MIN_H(0).LFBK));

FTCPE_MIN_H2: FTCPE port map (MIN_H(2),MIN_H_T(2),CLK_100,NOT CLR,'0');
MIN_H_T(2) <= (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	MIN_H(1).LFBK AND NOT MIN_L(1).LFBK AND NOT MIN_L(2).LFBK AND NOT MSEC_H(1).LFBK AND 
	NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND NOT SEC_H(3).LFBK AND 
	SEC_L(3).LFBK AND NOT MIN_H(2).LFBK AND MIN_H(0).LFBK);

FTCPE_MIN_L0: FTCPE port map (MIN_L(0),MIN_L_T(0),CLK_100,NOT CLR,'0');
MIN_L_T(0) <= (MSEC_L(0) AND SEC_H(0) AND NOT MSEC_H(1) AND NOT SEC_H(1) AND 
	NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND SEC_L(3) AND NOT PAUSE AND 
	MSEC_H(0).LFBK AND SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND 
	NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK);

FTCPE_MIN_L1: FTCPE port map (MIN_L(1),MIN_L_T(1),CLK_100,NOT CLR,'0');
MIN_L_T(1) <= ((MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND NOT MIN_L(3) AND 
	MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND 
	NOT SEC_H(3).LFBK AND SEC_L(3).LFBK)
	OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND 
	MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_L(1).LFBK AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND 
	NOT SEC_H(3).LFBK AND SEC_L(3).LFBK)
	OR (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND 
	MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_L(2).LFBK AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND 
	NOT SEC_H(3).LFBK AND SEC_L(3).LFBK));

FTCPE_MIN_L2: FTCPE port map (MIN_L(2),MIN_L_T(2),CLK_100,NOT CLR,'0');
MIN_L_T(2) <= (MSEC_L(0) AND MIN_L(0) AND MSEC_H(0) AND SEC_L(0) AND 
	NOT MSEC_H(2) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND 
	MSEC_L(3) AND NOT PAUSE AND SEC_H(0).LFBK AND MIN_L(1).LFBK AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND 
	NOT SEC_H(3).LFBK AND SEC_L(3).LFBK);

FTCPE_MIN_L3: FTCPE port map (MIN_L(3),MIN_L_T(3),CLK_100,NOT CLR,'0');
MIN_L_T(3) <= ((MSEC_L(0) AND SEC_H(0) AND MIN_L(1) AND MIN_L(2) AND 
	NOT MSEC_H(1) AND NOT SEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND 
	SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND 
	NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND 
	MSEC_H(3).LFBK AND MSEC_L(3).LFBK AND MIN_L(0).LFBK)
	OR (MSEC_L(0) AND SEC_H(0) AND NOT MIN_L(1) AND NOT MIN_L(2) AND 
	NOT MSEC_H(1) AND NOT SEC_H(1) AND NOT SEC_L(1) AND NOT SEC_L(2) AND NOT SEC_H(3) AND 
	SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND SEC_L(0).LFBK AND 
	NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND SEC_H(2).LFBK AND 
	MSEC_H(3).LFBK AND MSEC_L(3).LFBK AND MIN_L(0).LFBK AND MIN_L(3).LFBK));

FTCPE_MSEC_H0: FTCPE port map (MSEC_H(0),MSEC_H_T(0),CLK_100,NOT CLR,'0');
MSEC_H_T(0) <= (MSEC_L(0) AND NOT PAUSE AND NOT MSEC_L(1).LFBK AND 
	NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK);

FTCPE_MSEC_H1: FTCPE port map (MSEC_H(1),MSEC_H_T(1),CLK_100,NOT CLR,'0');
MSEC_H_T(1) <= ((MSEC_L(0) AND MSEC_H(0) AND MSEC_H(2) AND NOT MSEC_L(1) AND 
	NOT MSEC_L(2) AND MSEC_L(3) AND NOT PAUSE)
	OR (MSEC_L(0) AND MSEC_H(0) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND 
	NOT MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE)
	OR (MSEC_L(0) AND MSEC_H(0) AND NOT MSEC_L(1) AND NOT MSEC_L(2) AND 
	MSEC_L(3) AND NOT PAUSE AND MSEC_H(1).LFBK));

FTCPE_MSEC_H2: FTCPE port map (MSEC_H(2),MSEC_H_T(2),CLK_100,NOT CLR,'0');
MSEC_H_T(2) <= (MSEC_L(0) AND MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND 
	NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK);

FTCPE_MSEC_H3: FTCPE port map (MSEC_H(3),MSEC_H_T(3),CLK_100,NOT CLR,'0');
MSEC_H_T(3) <= ((MSEC_L(0) AND MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND 
	MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK)
	OR (MSEC_L(0) AND NOT MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND 
	NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_H(3).LFBK AND 
	MSEC_L(3).LFBK));

FTCPE_MSEC_L0: FTCPE port map (MSEC_L(0),PAUSE,CLK_100,NOT CLR,'0');

FTCPE_MSEC_L1: FTCPE port map (MSEC_L(1),MSEC_L_T(1),CLK_100,NOT CLR,'0');
MSEC_L_T(1) <= ((MSEC_L(0) AND NOT PAUSE AND MSEC_L(1).LFBK)
	OR (MSEC_L(0) AND NOT PAUSE AND MSEC_L(2).LFBK)
	OR (MSEC_L(0) AND NOT PAUSE AND NOT MSEC_L(3).LFBK));

FTCPE_MSEC_L2: FTCPE port map (MSEC_L(2),MSEC_L_T(2),CLK_100,NOT CLR,'0');
MSEC_L_T(2) <= (MSEC_L(0) AND NOT PAUSE AND MSEC_L(1).LFBK);

FTCPE_MSEC_L3: FTCPE port map (MSEC_L(3),MSEC_L_T(3),CLK_100,NOT CLR,'0');
MSEC_L_T(3) <= ((MSEC_L(0) AND NOT PAUSE AND MSEC_L(1).LFBK AND 
	MSEC_L(2).LFBK)
	OR (MSEC_L(0) AND NOT PAUSE AND NOT MSEC_L(1).LFBK AND 
	NOT MSEC_L(2).LFBK AND MSEC_L(3).LFBK));

FTCPE_SEC_H0: FTCPE port map (SEC_H(0),SEC_H_T(0),CLK_100,NOT CLR,'0');
SEC_H_T(0) <= (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK);

FTCPE_SEC_H1: FTCPE port map (SEC_H(1),SEC_H_T(1),CLK_100,NOT CLR,'0');
SEC_H_T(1) <= ((MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND NOT SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND 
	NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND 
	NOT SEC_L(2).LFBK AND SEC_L(3).LFBK)
	OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND SEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND 
	NOT SEC_L(2).LFBK AND SEC_L(3).LFBK)
	OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND 
	SEC_H(3).LFBK AND SEC_L(3).LFBK));

FTCPE_SEC_H2: FTCPE port map (SEC_H(2),SEC_H_T(2),CLK_100,NOT CLR,'0');
SEC_H_T(2) <= ((MSEC_L(0) AND SEC_H(0) AND NOT MSEC_H(1) AND SEC_H(1) AND 
	NOT SEC_L(1) AND NOT SEC_L(2) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND 
	SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND 
	MSEC_H(3).LFBK AND MSEC_L(3).LFBK)
	OR (MSEC_L(0) AND SEC_H(0) AND NOT MSEC_H(1) AND NOT SEC_L(1) AND 
	NOT SEC_L(2) AND NOT SEC_H(3) AND SEC_L(3) AND NOT PAUSE AND MSEC_H(0).LFBK AND 
	SEC_L(0).LFBK AND NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND 
	SEC_H(2).LFBK AND MSEC_H(3).LFBK AND MSEC_L(3).LFBK));

FTCPE_SEC_H3: FTCPE port map (SEC_H(3),SEC_H_T(3),CLK_100,NOT CLR,'0');
SEC_H_T(3) <= (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND SEC_H(2) AND MSEC_H(3) AND MSEC_L(3) AND 
	NOT PAUSE AND SEC_H(0).LFBK AND NOT MSEC_H(1).LFBK AND SEC_H(1).LFBK AND 
	NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK);

FTCPE_SEC_L0: FTCPE port map (SEC_L(0),SEC_L_T(0),CLK_100,NOT CLR,'0');
SEC_L_T(0) <= (MSEC_L(0) AND NOT MSEC_H(1) AND NOT PAUSE AND MSEC_H(0).LFBK AND 
	NOT MSEC_H(2).LFBK AND NOT MSEC_L(1).LFBK AND NOT MSEC_L(2).LFBK AND MSEC_H(3).LFBK AND 
	MSEC_L(3).LFBK);

FTCPE_SEC_L1: FTCPE port map (SEC_L(1),SEC_L_T(1),CLK_100,NOT CLR,'0');
SEC_L_T(1) <= ((MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND SEC_L(1).LFBK)
	OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND SEC_L(2).LFBK)
	OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_L(3).LFBK));

FTCPE_SEC_L2: FTCPE port map (SEC_L(2),SEC_L_T(2),CLK_100,NOT CLR,'0');
SEC_L_T(2) <= (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND SEC_L(1).LFBK);

FTCPE_SEC_L3: FTCPE port map (SEC_L(3),SEC_L_T(3),CLK_100,NOT CLR,'0');
SEC_L_T(3) <= ((MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND SEC_L(1).LFBK AND SEC_L(2).LFBK)
	OR (MSEC_L(0) AND MSEC_H(0) AND SEC_L(0) AND NOT MSEC_H(2) AND 
	NOT MSEC_L(1) AND NOT MSEC_L(2) AND MSEC_H(3) AND MSEC_L(3) AND NOT PAUSE AND 
	NOT MSEC_H(1).LFBK AND NOT SEC_L(1).LFBK AND NOT SEC_L(2).LFBK AND SEC_L(3).LFBK));


SEG_I(0) <= NOT (((NOT SEG_BUF(1) AND SEG_BUF(2) AND NOT SEG_BUF(0) AND 
	NOT SEG_BUF(3))
	OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND SEG_BUF(0) AND 
	NOT SEG_BUF(3))));
SEG(0) <= SEG_I(0) when SEG_OE(0) = '1' else 'Z';
SEG_OE(0) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST.LFBK;


SEG_I(1) <= NOT (((SEG_BUF(1) AND SEG_BUF(2) AND NOT SEG_BUF(0) AND 
	NOT SEG_BUF(3))
	OR (NOT SEG_BUF(1) AND SEG_BUF(2) AND SEG_BUF(0) AND 
	NOT SEG_BUF(3))));
SEG(1) <= SEG_I(1) when SEG_OE(1) = '1' else 'Z';
SEG_OE(1) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST.LFBK;


SEG_I(2) <= NOT ((SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(0) AND 
	NOT SEG_BUF(3)));
SEG(2) <= SEG_I(2) when SEG_OE(2) = '1' else 'Z';
SEG_OE(2) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST;


SEG_I(3) <= NOT (((SEG_BUF(1) AND SEG_BUF(2) AND SEG_BUF(0) AND 
	NOT SEG_BUF(3))
	OR (NOT SEG_BUF(1) AND SEG_BUF(2) AND NOT SEG_BUF(0) AND 
	NOT SEG_BUF(3))
	OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND SEG_BUF(0) AND 
	NOT SEG_BUF(3))));
SEG(3) <= SEG_I(3) when SEG_OE(3) = '1' else 'Z';
SEG_OE(3) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST;


SEG_I(4) <= ((SEG_BUF(1) AND NOT SEG_BUF(0) AND NOT SEG_BUF(3))
	OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(0)));
SEG(4) <= SEG_I(4) when SEG_OE(4) = '1' else 'Z';
SEG_OE(4) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST;


SEG_I(5) <= NOT (((SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(3))
	OR (SEG_BUF(1) AND SEG_BUF(0) AND NOT SEG_BUF(3))
	OR (NOT SEG_BUF(2) AND SEG_BUF(0) AND NOT SEG_BUF(3))));
SEG(5) <= SEG_I(5) when SEG_OE(5) = '1' else 'Z';
SEG_OE(5) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST;


SEG_I(6) <= NOT (((NOT SEG_BUF(1) AND NOT SEG_BUF(2) AND NOT SEG_BUF(3))
	OR (SEG_BUF(1) AND SEG_BUF(2) AND SEG_BUF(0) AND 
	NOT SEG_BUF(3))));
SEG(6) <= SEG_I(6) when SEG_OE(6) = '1' else 'Z';
SEG_OE(6) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST;


SEG_I(7) <= '0';
SEG(7) <= SEG_I(7) when SEG_OE(7) = '1' else 'Z';
SEG_OE(7) <= SEG_6_OBUFE/SEG_6_OBUFE_TRST;


SEG_6_OBUFE/SEG_6_OBUFE_TRST <= ((NOT SEG_BUF(3))
	OR (NOT SEG_BUF(1) AND NOT SEG_BUF(2)));


SEG_BUF(0)/SEG_BUF(0)_RSTF <= ((EXP0_.EXP)
	OR (NOT MSEC_L(0) AND NOT COUNTER(9) AND NOT COUNTER(11) AND 
	NOT COUNTER(10))
	OR (NOT SEC_H(0) AND COUNTER(9) AND NOT COUNTER(11) AND 
	COUNTER(10))
	OR (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND 
	NOT MSEC_H(0).LFBK)
	OR (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10) AND 
	NOT MIN_L(0).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10) AND 
	NOT SEC_L(0).LFBK));

FDCPE_SEG_BUF0: FDCPE port map (SEG_BUF(0),'0','0',SEG_BUF(0)/SEG_BUF(0)_RSTF,SEG_BUF_PRE(0));
SEG_BUF_PRE(0) <= (NOT $OpTx$$OpTx$FX_DC$51_INV$198 AND 
	NOT SEG_BUF(0)/SEG_BUF(0)_RSTF);

FDCPE_SEG_BUF1: FDCPE port map (SEG_BUF(1),'0','0',SEG_BUF(1)/SEG_BUF(1)_RSTF,SEG_BUF_PRE(1));
SEG_BUF_PRE(1) <= (NOT SEG_BUF(1)/SEG_BUF(1)_RSTF AND 
	NOT $OpTx$$OpTx$FX_DC$51_INV$198);


SEG_BUF(1)/SEG_BUF(1)_RSTF <= ((SEL_2.EXP)
	OR (NOT MSEC_L(1) AND NOT COUNTER(9) AND NOT COUNTER(11) AND 
	NOT COUNTER(10))
	OR (COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10) AND 
	NOT SEC_H(1).LFBK)
	OR (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND 
	NOT MSEC_H(1).LFBK)
	OR (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10) AND 
	NOT MIN_L(1).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10) AND 
	NOT SEC_L(1).LFBK));

FDCPE_SEG_BUF2: FDCPE port map (SEG_BUF(2),'0','0',SEG_BUF(2)/SEG_BUF(2)_RSTF,SEG_BUF_PRE(2));
SEG_BUF_PRE(2) <= (NOT $OpTx$$OpTx$FX_DC$51_INV$198 AND 
	NOT SEG_BUF(2)/SEG_BUF(2)_RSTF);


SEG_BUF(2)/SEG_BUF(2)_RSTF <= ((SEL_1/SEL_1_RSTF__$INT.EXP)
	OR (NOT MIN_L(2) AND NOT COUNTER(10) AND NOT COUNTER(9).LFBK AND 
	COUNTER(11).LFBK)
	OR (NOT MSEC_H(2) AND NOT COUNTER(10) AND COUNTER(9).LFBK AND 
	NOT COUNTER(11).LFBK)
	OR (NOT MSEC_L(2) AND NOT COUNTER(10) AND NOT COUNTER(9).LFBK AND 
	NOT COUNTER(11).LFBK)
	OR (NOT SEC_H(2) AND COUNTER(10) AND COUNTER(9).LFBK AND 
	NOT COUNTER(11).LFBK)
	OR (NOT SEC_L(2) AND COUNTER(10) AND NOT COUNTER(9).LFBK AND 
	NOT COUNTER(11).LFBK));

FDCPE_SEG_BUF3: FDCPE port map (SEG_BUF(3),'0','0',SEG_BUF_CLR(3),SEG_BUF(3)/SEG_BUF(3)_SETF);
SEG_BUF_CLR(3) <= (NOT $OpTx$$OpTx$FX_DC$51_INV$198 AND 
	NOT SEG_BUF(3)/SEG_BUF(3)_SETF);


SEG_BUF(3)/SEG_BUF(3)_SETF <= ((SEC_H(3) AND COUNTER(9) AND NOT COUNTER(11) AND 
	COUNTER(10))
	OR (SEC_L(3) AND NOT COUNTER(9) AND NOT COUNTER(11) AND 
	COUNTER(10))
	OR (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND 
	MSEC_H(3).LFBK)
	OR (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10) AND 
	MIN_L(3).LFBK)
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10) AND 
	MSEC_L(3).LFBK));

FDCPE_SEL0: FDCPE port map (SEL(0),'0','0',NOT SEL_0/SEL_0_RSTF__$INT,SEL_PRE(0));
SEL_PRE(0) <= (NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10));

FDCPE_SEL1: FDCPE port map (SEL(1),'0','0',NOT SEL_1/SEL_1_RSTF__$INT,SEL_PRE(1));
SEL_PRE(1) <= (COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10));

FDCPE_SEL2: FDCPE port map (SEL(2),'0','0',NOT SEL_2/SEL_2_RSTF__$INT,SEL_PRE(2));
SEL_PRE(2) <= (NOT COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10));

FDCPE_SEL3: FDCPE port map (SEL(3),'0','0',NOT SEL_3/SEL_3_RSTF__$INT,SEL_PRE(3));
SEL_PRE(3) <= (COUNTER(9) AND NOT COUNTER(11) AND COUNTER(10).LFBK);

FDCPE_SEL4: FDCPE port map (SEL(4),'0','0',NOT SEL_4/SEL_4_RSTF__$INT,SEL_PRE(4));
SEL_PRE(4) <= (NOT COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10).LFBK);

FDCPE_SEL5: FDCPE port map (SEL(5),'0','0',NOT SEL_5/SEL_5_RSTF__$INT,SEL_PRE(5));
SEL_PRE(5) <= (COUNTER(9) AND COUNTER(11) AND NOT COUNTER(10).LFBK);


SEL_0/SEL_0_RSTF__$INT <= ((COUNTER(9) AND COUNTER(11) AND COUNTER(10))
	OR (NOT COUNTER(9) AND NOT COUNTER(11) AND NOT COUNTER(10)));


SEL_1/SEL_1_RSTF__$INT <= ((COUNTER(10) AND COUNTER(9).LFBK AND COUNTER(11).LFBK)
	OR (NOT COUNTER(10) AND COUNTER(9).LFBK AND NOT COUNTER(11).LFBK));


SEL_2/SEL_2_RSTF__$INT <= ((COUNTER(10) AND COUNTER(9).LFBK AND COUNTER(11).LFBK)
	OR (COUNTER(10) AND NOT COUNTER(9).LFBK AND NOT COUNTER(11).LFBK));


SEL_3/SEL_3_RSTF__$INT <= (COUNTER(10) AND COUNTER(9).LFBK);


SEL_4/SEL_4_RSTF__$INT <= ((COUNTER(10) AND COUNTER(9).LFBK AND COUNTER(11).LFBK)
	OR (NOT COUNTER(10) AND NOT COUNTER(9).LFBK AND COUNTER(11).LFBK));


SEL_5/SEL_5_RSTF__$INT <= (COUNTER(9) AND COUNTER(11));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


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  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              43 TIE                           
  2 TIE                              44 TIE                           
  3 TIE                              45 TIE                           
  4 TIE                              46 TIE                           
  5 TIE                              47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 CLK                              51 TIE                           
 10 TIE                              52 TIE                           
 11 TIE                              53 TIE                           
 12 TIE                              54 SEL<0>                        
 13 TIE                              55 SEL<1>                        
 14 TIE                              56 SEL<2>                        
 15 TIE                              57 SEL<3>                        
 16 GND                              58 SEL<4>                        
 17 TIE                              59 TDO                           
 18 TIE                              60 GND                           
 19 TIE                              61 SEL<5>                        
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 SEG<7>                        
 24 TIE                              66 SEG<6>                        
 25 TIE                              67 SEG<5>                        
 26 TIE                              68 SEG<4>                        
 27 GND                              69 SEG<3>                        
 28 TDI                              70 SEG<2>                        
 29 TMS                              71 SEG<1>                        
 30 TCK                              72 SEG<0>                        
 31 TIE                              73 VCC                           
 32 TIE                              74 CLR                           
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 PAUSE                            78 VCC                           
 37 TIE                              79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 TIE                           
 40 TIE                              82 TIE                           
 41 TIE                              83 TIE                           
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25