Timing Report

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Design Name CPLD_MCU_RW
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Sat Apr 24 16:52:40 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for ALE
Clock to Setup (tCYC) 9.000 ns.
Pad to Pad Delay (tPD) 10.000 ns.
Setup to Clock at the Pad (tSU) 2.000 ns.
Clock Pad to Output Pad Delay (tCO) 23.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 15.0 80 80
AUTO_TS_P2P 0.0 23.0 24 24
AUTO_TS_P2F 0.0 8.5 49 49
AUTO_TS_F2P 0.0 16.5 16 16


Constraint: TS1000

Description: PERIOD:PERIOD_ALE:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_WR:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_RD:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CONTROL_REG<0>.Q to LED<0>.D 0.000 15.000 -15.000
CONTROL_REG<0>.Q to LED<1>.D 0.000 15.000 -15.000
CONTROL_REG<0>.Q to LED<2>.D 0.000 15.000 -15.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
RD to DATA_PORT<0> 0.000 23.000 -23.000
RD to DATA_PORT<1> 0.000 23.000 -23.000
RD to DATA_PORT<2> 0.000 23.000 -23.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
DATA_PORT<0> to CONTROL_REG<0>.D 0.000 8.500 -8.500
DATA_PORT<0> to LED<0>.D 0.000 8.500 -8.500
DATA_PORT<1> to CONTROL_REG<1>.D 0.000 8.500 -8.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
KEY_REG<0>.Q to DATA_PORT<0> 0.000 16.500 -16.500
KEY_REG<1>.Q to DATA_PORT<1> 0.000 16.500 -16.500
KEY_REG<2>.Q to DATA_PORT<2> 0.000 16.500 -16.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
ALE 83.333 Limited by Clock Pulse Width for ALE
WR 83.333 Limited by Clock Pulse Width for WR
RD 83.333 Limited by Clock Pulse Width for RD

Setup/Hold Times for Clocks

Setup/Hold Times for Clock ALE
Source Pad Setup to clk (edge) Hold to clk (edge)
DATA_PORT<0> 2.000 1.500
DATA_PORT<1> 2.000 1.500
DATA_PORT<2> 2.000 1.500
DATA_PORT<3> 2.000 1.500
DATA_PORT<4> 2.000 1.500
DATA_PORT<5> 2.000 1.500
DATA_PORT<6> 2.000 1.500
DATA_PORT<7> 2.000 1.500

Setup/Hold Times for Clock WR
Source Pad Setup to clk (edge) Hold to clk (edge)
DATA_PORT<0> 2.000 1.500
DATA_PORT<1> 2.000 1.500
DATA_PORT<2> 2.000 1.500
DATA_PORT<3> 2.000 1.500
DATA_PORT<4> 2.000 1.500
DATA_PORT<5> 2.000 1.500
DATA_PORT<6> 2.000 1.500
DATA_PORT<7> 2.000 1.500

Setup/Hold Times for Clock RD
Source Pad Setup to clk (edge) Hold to clk (edge)
KEY<0> 2.000 1.500
KEY<1> 2.000 1.500
KEY<2> 2.000 1.500
KEY<3> 2.000 1.500
KEY<4> 2.000 1.500
KEY<5> 2.000 1.500
KEY<6> 2.000 1.500
KEY<7> 2.000 1.500


Clock to Pad Timing

Clock WR to Pad
Destination Pad Clock (edge) to Pad
LED<0> 10.000
LED<1> 10.000
LED<2> 10.000
LED<3> 10.000
LED<4> 10.000
LED<5> 10.000
LED<6> 10.000
LED<7> 10.000

Clock RD to Pad
Destination Pad Clock (edge) to Pad
DATA_PORT<0> 23.000
DATA_PORT<1> 23.000
DATA_PORT<2> 23.000
DATA_PORT<3> 23.000
DATA_PORT<4> 23.000
DATA_PORT<5> 23.000
DATA_PORT<6> 23.000
DATA_PORT<7> 23.000


Clock to Setup Times for Clocks

Clock to Setup for clock WR
Source Destination Delay
LED<0>.Q LED<0>.D 9.000
LED<1>.Q LED<1>.D 9.000
LED<2>.Q LED<2>.D 9.000
LED<3>.Q LED<3>.D 9.000
LED<4>.Q LED<4>.D 9.000
LED<5>.Q LED<5>.D 9.000
LED<6>.Q LED<6>.D 9.000
LED<7>.Q LED<7>.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay
RD DATA_PORT<0> 10.000
RD DATA_PORT<1> 10.000
RD DATA_PORT<2> 10.000
RD DATA_PORT<3> 10.000
RD DATA_PORT<4> 10.000
RD DATA_PORT<5> 10.000
RD DATA_PORT<6> 10.000
RD DATA_PORT<7> 10.000



Number of paths analyzed: 169
Number of Timing errors: 169
Analysis Completed: Sat Apr 24 16:52:40 2010