Timing Report

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Design Name LCD_TEST
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Sat Apr 24 15:57:07 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 17.000 ns.
Max. Clock Frequency (fSYSTEM) 58.824 MHz.
Limited by Cycle Time for CLK_LOW.Q
Clock to Setup (tCYC) 17.000 ns.
Clock Pad to Output Pad Delay (tCO) 29.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
AUTO_TS_F2F 0.0 17.0 233 233
AUTO_TS_P2P 0.0 29.0 10 10
AUTO_TS_P2F 0.0 2.5 1 1
AUTO_TS_F2P 0.0 16.5 10 10


Constraint: TS1000

Description: PERIOD:PERIOD_CLK_LOW.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CURRENT<0>.Q to LCD_DATA<0>.D 0.000 17.000 -17.000
CURRENT<0>.Q to LCD_DATA<1>.D 0.000 17.000 -17.000
CURRENT<0>.Q to LCD_DATA<3>.D 0.000 17.000 -17.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to LCD_DATA<2> 0.000 29.000 -29.000
CLK to LCD_DATA<4> 0.000 23.000 -23.000
CLK to LCD_DATA<6> 0.000 23.000 -23.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to FCLKIO_0 0.000 2.500 -2.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
LCD_DATA<2>_BUFR.Q to LCD_DATA<2> 0.000 16.500 -16.500
LCD_DATA<4>_BUFR.Q to LCD_DATA<4> 0.000 10.500 -10.500
LCD_DATA<6>_BUFR.Q to LCD_DATA<6> 0.000 10.500 -10.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK_LOW.Q 58.824 Limited by Cycle Time for CLK_LOW.Q
CLK 66.667 Limited by Cycle Time for CLK

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
LCD_DATA<2> 29.000
LCD_DATA<4> 23.000
LCD_DATA<6> 23.000
LCD_DATA<5> 16.000
LCD_DATA<7> 16.000
LCD_DATA<0> 13.000
LCD_DATA<1> 13.000
LCD_DATA<3> 13.000
RS 13.000
EN 6.000


Clock to Setup Times for Clocks

Clock to Setup for clock EN.Q
Source Destination Delay
CURRENT<0>.Q LCD_DATA<0>.D 17.000
CURRENT<0>.Q LCD_DATA<1>.D 17.000
CURRENT<0>.Q LCD_DATA<3>.D 17.000
CURRENT<1>.Q LCD_DATA<0>.D 17.000
CURRENT<1>.Q LCD_DATA<1>.D 17.000
CURRENT<1>.Q LCD_DATA<3>.D 17.000
CURRENT<2>.Q LCD_DATA<0>.D 17.000
CURRENT<2>.Q LCD_DATA<1>.D 17.000
CURRENT<2>.Q LCD_DATA<3>.D 17.000
CURRENT<3>.Q LCD_DATA<0>.D 17.000
CURRENT<3>.Q LCD_DATA<1>.D 17.000
CURRENT<3>.Q LCD_DATA<3>.D 17.000
CURRENT<4>.Q LCD_DATA<0>.D 17.000
CURRENT<4>.Q LCD_DATA<1>.D 17.000
CURRENT<4>.Q LCD_DATA<3>.D 17.000
CURRENT<5>.Q LCD_DATA<0>.D 17.000
CURRENT<5>.Q LCD_DATA<1>.D 17.000
CURRENT<5>.Q LCD_DATA<3>.D 17.000
CURRENT<0>.Q LCD_DATA<4>_BUFR.D 16.000
CURRENT<0>.Q LCD_DATA<5>.D 16.000
CURRENT<0>.Q LCD_DATA<6>_BUFR.D 16.000
CURRENT<0>.Q LCD_DATA<7>.D 16.000
CURRENT<0>.Q RS.D 16.000
CURRENT<1>.Q LCD_DATA<4>_BUFR.D 16.000
CURRENT<1>.Q LCD_DATA<5>.D 16.000
CURRENT<1>.Q LCD_DATA<6>_BUFR.D 16.000
CURRENT<1>.Q LCD_DATA<7>.D 16.000
CURRENT<1>.Q RS.D 16.000
CURRENT<2>.Q LCD_DATA<4>_BUFR.D 16.000
CURRENT<2>.Q LCD_DATA<5>.D 16.000
CURRENT<2>.Q LCD_DATA<6>_BUFR.D 16.000
CURRENT<2>.Q LCD_DATA<7>.D 16.000
CURRENT<2>.Q RS.D 16.000
CURRENT<3>.Q LCD_DATA<4>_BUFR.D 16.000
CURRENT<3>.Q LCD_DATA<5>.D 16.000
CURRENT<3>.Q LCD_DATA<6>_BUFR.D 16.000
CURRENT<3>.Q LCD_DATA<7>.D 16.000
CURRENT<3>.Q RS.D 16.000
CURRENT<4>.Q LCD_DATA<4>_BUFR.D 16.000
CURRENT<4>.Q LCD_DATA<5>.D 16.000
CURRENT<4>.Q LCD_DATA<6>_BUFR.D 16.000
CURRENT<4>.Q LCD_DATA<7>.D 16.000
CURRENT<4>.Q RS.D 16.000
CURRENT<5>.Q LCD_DATA<4>_BUFR.D 16.000
CURRENT<5>.Q LCD_DATA<5>.D 16.000
CURRENT<5>.Q LCD_DATA<6>_BUFR.D 16.000
CURRENT<5>.Q LCD_DATA<7>.D 16.000
CURRENT<5>.Q RS.D 16.000
LCD_DATA<1>.Q LCD_DATA<1>.D 11.000
CURRENT<0>.Q LCD_DATA<2>_BUFR.D 10.000
CURRENT<1>.Q LCD_DATA<2>_BUFR.D 10.000
CURRENT<2>.Q LCD_DATA<2>_BUFR.D 10.000
CURRENT<3>.Q LCD_DATA<2>_BUFR.D 10.000
CURRENT<4>.Q LCD_DATA<2>_BUFR.D 10.000
CURRENT<5>.Q LCD_DATA<2>_BUFR.D 10.000
LCD_DATA<0>.Q LCD_DATA<0>.D 10.000
LCD_DATA<2>_BUFR.Q LCD_DATA<2>_BUFR.D 10.000
LCD_DATA<3>.Q LCD_DATA<3>.D 10.000
LCD_DATA<4>_BUFR.Q LCD_DATA<4>_BUFR.D 10.000
LCD_DATA<5>.Q LCD_DATA<5>.D 10.000
LCD_DATA<6>_BUFR.Q LCD_DATA<6>_BUFR.D 10.000
LCD_DATA<7>.Q LCD_DATA<7>.D 10.000
RS.Q RS.D 10.000
CURRENT<0>.Q CURRENT<0>.D 9.000
CURRENT<0>.Q CURRENT<1>.D 9.000
CURRENT<0>.Q CURRENT<2>.D 9.000
CURRENT<0>.Q CURRENT<3>.D 9.000
CURRENT<0>.Q CURRENT<4>.D 9.000
CURRENT<0>.Q CURRENT<5>.D 9.000
CURRENT<1>.Q CURRENT<0>.D 9.000
CURRENT<1>.Q CURRENT<1>.D 9.000
CURRENT<1>.Q CURRENT<2>.D 9.000
CURRENT<1>.Q CURRENT<3>.D 9.000
CURRENT<1>.Q CURRENT<4>.D 9.000
CURRENT<1>.Q CURRENT<5>.D 9.000
CURRENT<2>.Q CURRENT<0>.D 9.000
CURRENT<2>.Q CURRENT<2>.D 9.000
CURRENT<2>.Q CURRENT<3>.D 9.000
CURRENT<2>.Q CURRENT<4>.D 9.000
CURRENT<2>.Q CURRENT<5>.D 9.000
CURRENT<3>.Q CURRENT<0>.D 9.000
CURRENT<3>.Q CURRENT<1>.D 9.000
CURRENT<3>.Q CURRENT<2>.D 9.000
CURRENT<3>.Q CURRENT<3>.D 9.000
CURRENT<3>.Q CURRENT<4>.D 9.000
CURRENT<3>.Q CURRENT<5>.D 9.000
CURRENT<4>.Q CURRENT<0>.D 9.000
CURRENT<4>.Q CURRENT<1>.D 9.000
CURRENT<4>.Q CURRENT<2>.D 9.000
CURRENT<4>.Q CURRENT<4>.D 9.000
CURRENT<4>.Q CURRENT<5>.D 9.000
CURRENT<5>.Q CURRENT<0>.D 9.000
CURRENT<5>.Q CURRENT<1>.D 9.000
CURRENT<5>.Q CURRENT<2>.D 9.000
CURRENT<5>.Q CURRENT<3>.D 9.000
CURRENT<5>.Q CURRENT<4>.D 9.000
CURRENT<5>.Q CURRENT<5>.D 9.000

Clock to Setup for clock CLK
Source Destination Delay
COUNTER<0>.Q COUNTER<10>.D 15.000
COUNTER<0>.Q COUNTER<11>.D 15.000
COUNTER<0>.Q COUNTER<12>.D 15.000
COUNTER<0>.Q COUNTER<13>.D 15.000
COUNTER<0>.Q COUNTER<14>.D 15.000
COUNTER<0>.Q COUNTER<15>.D 15.000
COUNTER<0>.Q COUNTER<8>.D 15.000
COUNTER<0>.Q COUNTER<9>.D 15.000
COUNTER<0>.Q EN.D 15.000
COUNTER<1>.Q COUNTER<10>.D 15.000
COUNTER<1>.Q COUNTER<11>.D 15.000
COUNTER<1>.Q COUNTER<12>.D 15.000
COUNTER<1>.Q COUNTER<13>.D 15.000
COUNTER<1>.Q COUNTER<14>.D 15.000
COUNTER<1>.Q COUNTER<15>.D 15.000
COUNTER<1>.Q COUNTER<8>.D 15.000
COUNTER<1>.Q COUNTER<9>.D 15.000
COUNTER<1>.Q EN.D 15.000
COUNTER<2>.Q COUNTER<10>.D 15.000
COUNTER<2>.Q COUNTER<11>.D 15.000
COUNTER<2>.Q COUNTER<12>.D 15.000
COUNTER<2>.Q COUNTER<13>.D 15.000
COUNTER<2>.Q COUNTER<14>.D 15.000
COUNTER<2>.Q COUNTER<15>.D 15.000
COUNTER<2>.Q COUNTER<8>.D 15.000
COUNTER<2>.Q COUNTER<9>.D 15.000
COUNTER<2>.Q EN.D 15.000
COUNTER<3>.Q COUNTER<10>.D 15.000
COUNTER<3>.Q COUNTER<11>.D 15.000
COUNTER<3>.Q COUNTER<12>.D 15.000
COUNTER<3>.Q COUNTER<13>.D 15.000
COUNTER<3>.Q COUNTER<14>.D 15.000
COUNTER<3>.Q COUNTER<15>.D 15.000
COUNTER<3>.Q COUNTER<8>.D 15.000
COUNTER<3>.Q COUNTER<9>.D 15.000
COUNTER<3>.Q EN.D 15.000
COUNTER<4>.Q COUNTER<10>.D 15.000
COUNTER<4>.Q COUNTER<11>.D 15.000
COUNTER<4>.Q COUNTER<12>.D 15.000
COUNTER<4>.Q COUNTER<13>.D 15.000
COUNTER<4>.Q COUNTER<14>.D 15.000
COUNTER<4>.Q COUNTER<15>.D 15.000
COUNTER<4>.Q COUNTER<8>.D 15.000
COUNTER<4>.Q COUNTER<9>.D 15.000
COUNTER<4>.Q EN.D 15.000
COUNTER<5>.Q COUNTER<10>.D 15.000
COUNTER<5>.Q COUNTER<11>.D 15.000
COUNTER<5>.Q COUNTER<12>.D 15.000
COUNTER<5>.Q COUNTER<13>.D 15.000
COUNTER<5>.Q COUNTER<14>.D 15.000
COUNTER<5>.Q COUNTER<15>.D 15.000
COUNTER<5>.Q COUNTER<8>.D 15.000
COUNTER<5>.Q COUNTER<9>.D 15.000
COUNTER<5>.Q EN.D 15.000
COUNTER<6>.Q COUNTER<10>.D 15.000
COUNTER<6>.Q COUNTER<11>.D 15.000
COUNTER<6>.Q COUNTER<12>.D 15.000
COUNTER<6>.Q COUNTER<13>.D 15.000
COUNTER<6>.Q COUNTER<14>.D 15.000
COUNTER<6>.Q COUNTER<15>.D 15.000
COUNTER<6>.Q COUNTER<8>.D 15.000
COUNTER<6>.Q COUNTER<9>.D 15.000
COUNTER<6>.Q EN.D 15.000
COUNTER<7>.Q COUNTER<10>.D 15.000
COUNTER<7>.Q COUNTER<11>.D 15.000
COUNTER<7>.Q COUNTER<12>.D 15.000
COUNTER<7>.Q COUNTER<13>.D 15.000
COUNTER<7>.Q COUNTER<14>.D 15.000
COUNTER<7>.Q COUNTER<15>.D 15.000
COUNTER<7>.Q COUNTER<8>.D 15.000
COUNTER<7>.Q COUNTER<9>.D 15.000
COUNTER<7>.Q EN.D 15.000
COUNTER<0>.Q COUNTER<1>.D 9.000
COUNTER<0>.Q COUNTER<2>.D 9.000
COUNTER<0>.Q COUNTER<3>.D 9.000
COUNTER<0>.Q COUNTER<4>.D 9.000
COUNTER<0>.Q COUNTER<5>.D 9.000
COUNTER<0>.Q COUNTER<6>.D 9.000
COUNTER<0>.Q COUNTER<7>.D 9.000
COUNTER<10>.Q COUNTER<11>.D 9.000
COUNTER<10>.Q COUNTER<12>.D 9.000
COUNTER<10>.Q COUNTER<13>.D 9.000
COUNTER<10>.Q COUNTER<14>.D 9.000
COUNTER<10>.Q COUNTER<15>.D 9.000
COUNTER<10>.Q EN.D 9.000
COUNTER<11>.Q COUNTER<12>.D 9.000
COUNTER<11>.Q COUNTER<13>.D 9.000
COUNTER<11>.Q COUNTER<14>.D 9.000
COUNTER<11>.Q COUNTER<15>.D 9.000
COUNTER<11>.Q EN.D 9.000
COUNTER<12>.Q COUNTER<13>.D 9.000
COUNTER<12>.Q COUNTER<14>.D 9.000
COUNTER<12>.Q COUNTER<15>.D 9.000
COUNTER<12>.Q EN.D 9.000
COUNTER<13>.Q COUNTER<14>.D 9.000
COUNTER<13>.Q COUNTER<15>.D 9.000
COUNTER<13>.Q EN.D 9.000
COUNTER<14>.Q COUNTER<15>.D 9.000
COUNTER<14>.Q EN.D 9.000
COUNTER<15>.Q EN.D 9.000
COUNTER<1>.Q COUNTER<2>.D 9.000
COUNTER<1>.Q COUNTER<3>.D 9.000
COUNTER<1>.Q COUNTER<4>.D 9.000
COUNTER<1>.Q COUNTER<5>.D 9.000
COUNTER<1>.Q COUNTER<6>.D 9.000
COUNTER<1>.Q COUNTER<7>.D 9.000
COUNTER<2>.Q COUNTER<3>.D 9.000
COUNTER<2>.Q COUNTER<4>.D 9.000
COUNTER<2>.Q COUNTER<5>.D 9.000
COUNTER<2>.Q COUNTER<6>.D 9.000
COUNTER<2>.Q COUNTER<7>.D 9.000
COUNTER<3>.Q COUNTER<4>.D 9.000
COUNTER<3>.Q COUNTER<5>.D 9.000
COUNTER<3>.Q COUNTER<6>.D 9.000
COUNTER<3>.Q COUNTER<7>.D 9.000
COUNTER<4>.Q COUNTER<5>.D 9.000
COUNTER<4>.Q COUNTER<6>.D 9.000
COUNTER<4>.Q COUNTER<7>.D 9.000
COUNTER<5>.Q COUNTER<6>.D 9.000
COUNTER<5>.Q COUNTER<7>.D 9.000
COUNTER<6>.Q COUNTER<7>.D 9.000
COUNTER<8>.Q COUNTER<10>.D 9.000
COUNTER<8>.Q COUNTER<11>.D 9.000
COUNTER<8>.Q COUNTER<12>.D 9.000
COUNTER<8>.Q COUNTER<13>.D 9.000
COUNTER<8>.Q COUNTER<14>.D 9.000
COUNTER<8>.Q COUNTER<15>.D 9.000
COUNTER<8>.Q COUNTER<9>.D 9.000
COUNTER<8>.Q EN.D 9.000
COUNTER<9>.Q COUNTER<10>.D 9.000
COUNTER<9>.Q COUNTER<11>.D 9.000
COUNTER<9>.Q COUNTER<12>.D 9.000
COUNTER<9>.Q COUNTER<13>.D 9.000
COUNTER<9>.Q COUNTER<14>.D 9.000
COUNTER<9>.Q COUNTER<15>.D 9.000
COUNTER<9>.Q EN.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 254
Number of Timing errors: 254
Analysis Completed: Sat Apr 24 15:57:07 2010