Timing Report

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Design Name STOPWATCH
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Fri Apr 23 20:21:44 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 16.000 ns.
Max. Clock Frequency (fSYSTEM) 62.500 MHz.
Limited by Cycle Time for CLK
Clock to Setup (tCYC) 16.000 ns.
Setup to Clock at the Pad (tSU) -4.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
AUTO_TS_F2F 0.0 16.0 497 497
AUTO_TS_P2P 0.0 0.0 0 0
AUTO_TS_P2F 0.0 8.5 24 24
AUTO_TS_F2P 0.0 0.0 0 0


Constraint: TS1000

Description: PERIOD:PERIOD_SEL_5.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_SEL_4.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_SEL_3.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_SEL_2.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_SEL_1.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_SEL_0.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_SEG_BUF<3>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_SEG_BUF<0>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_SEG_BUF<2>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_SEG_BUF<1>.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_CLK_100.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
COUNTER<11>.Q to COUNTER<6>.D 0.000 16.000 -16.000
COUNTER<13>.Q to COUNTER<6>.D 0.000 16.000 -16.000
COUNTER<17>.Q to COUNTER<6>.D 0.000 16.000 -16.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
PAUSE to MIN_H<0>.D 0.000 8.500 -8.500
PAUSE to MIN_H<1>.D 0.000 8.500 -8.500
PAUSE to MIN_H<2>.D 0.000 8.500 -8.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 2

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 62.500 Limited by Cycle Time for CLK
CLK_100.Q 66.667 Limited by Cycle Time for CLK_100.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK_100.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
PAUSE -4.500 8.000


Clock to Pad Timing


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
COUNTER<11>.Q COUNTER<6>.D 16.000
COUNTER<13>.Q COUNTER<6>.D 16.000
COUNTER<17>.Q COUNTER<6>.D 16.000
COUNTER<5>.Q COUNTER<6>.D 16.000
COUNTER<8>.Q COUNTER<6>.D 16.000
COUNTER<9>.Q COUNTER<6>.D 16.000
COUNTER<0>.Q CLK_100.D 15.000
COUNTER<0>.Q COUNTER<10>.D 15.000
COUNTER<0>.Q COUNTER<11>.D 15.000
COUNTER<0>.Q COUNTER<12>.D 15.000
COUNTER<0>.Q COUNTER<13>.D 15.000
COUNTER<0>.Q COUNTER<14>.D 15.000
COUNTER<0>.Q COUNTER<15>.D 15.000
COUNTER<0>.Q COUNTER<16>.D 15.000
COUNTER<0>.Q COUNTER<17>.D 15.000
COUNTER<0>.Q COUNTER<2>.D 15.000
COUNTER<0>.Q COUNTER<3>.D 15.000
COUNTER<0>.Q COUNTER<4>.D 15.000
COUNTER<0>.Q COUNTER<5>.D 15.000
COUNTER<0>.Q COUNTER<6>.D 15.000
COUNTER<0>.Q COUNTER<7>.D 15.000
COUNTER<0>.Q COUNTER<8>.D 15.000
COUNTER<0>.Q COUNTER<9>.D 15.000
COUNTER<10>.Q CLK_100.D 15.000
COUNTER<10>.Q COUNTER<11>.D 15.000
COUNTER<10>.Q COUNTER<13>.D 15.000
COUNTER<10>.Q COUNTER<17>.D 15.000
COUNTER<11>.Q COUNTER<10>.D 15.000
COUNTER<11>.Q COUNTER<12>.D 15.000
COUNTER<11>.Q COUNTER<14>.D 15.000
COUNTER<11>.Q COUNTER<15>.D 15.000
COUNTER<11>.Q COUNTER<16>.D 15.000
COUNTER<11>.Q COUNTER<7>.D 15.000
COUNTER<12>.Q CLK_100.D 15.000
COUNTER<12>.Q COUNTER<13>.D 15.000
COUNTER<12>.Q COUNTER<17>.D 15.000
COUNTER<13>.Q COUNTER<10>.D 15.000
COUNTER<13>.Q COUNTER<12>.D 15.000
COUNTER<13>.Q COUNTER<14>.D 15.000
COUNTER<13>.Q COUNTER<15>.D 15.000
COUNTER<13>.Q COUNTER<16>.D 15.000
COUNTER<13>.Q COUNTER<7>.D 15.000
COUNTER<14>.Q CLK_100.D 15.000
COUNTER<14>.Q COUNTER<17>.D 15.000
COUNTER<15>.Q CLK_100.D 15.000
COUNTER<15>.Q COUNTER<17>.D 15.000
COUNTER<16>.Q CLK_100.D 15.000
COUNTER<16>.Q COUNTER<17>.D 15.000
COUNTER<17>.Q COUNTER<10>.D 15.000
COUNTER<17>.Q COUNTER<12>.D 15.000
COUNTER<17>.Q COUNTER<14>.D 15.000
COUNTER<17>.Q COUNTER<15>.D 15.000
COUNTER<17>.Q COUNTER<16>.D 15.000
COUNTER<17>.Q COUNTER<7>.D 15.000
COUNTER<1>.Q CLK_100.D 15.000
COUNTER<1>.Q COUNTER<10>.D 15.000
COUNTER<1>.Q COUNTER<11>.D 15.000
COUNTER<1>.Q COUNTER<12>.D 15.000
COUNTER<1>.Q COUNTER<13>.D 15.000
COUNTER<1>.Q COUNTER<14>.D 15.000
COUNTER<1>.Q COUNTER<15>.D 15.000
COUNTER<1>.Q COUNTER<16>.D 15.000
COUNTER<1>.Q COUNTER<17>.D 15.000
COUNTER<1>.Q COUNTER<2>.D 15.000
COUNTER<1>.Q COUNTER<3>.D 15.000
COUNTER<1>.Q COUNTER<4>.D 15.000
COUNTER<1>.Q COUNTER<5>.D 15.000
COUNTER<1>.Q COUNTER<6>.D 15.000
COUNTER<1>.Q COUNTER<7>.D 15.000
COUNTER<1>.Q COUNTER<8>.D 15.000
COUNTER<1>.Q COUNTER<9>.D 15.000
COUNTER<2>.Q COUNTER<10>.D 15.000
COUNTER<2>.Q COUNTER<12>.D 15.000
COUNTER<2>.Q COUNTER<14>.D 15.000
COUNTER<2>.Q COUNTER<15>.D 15.000
COUNTER<2>.Q COUNTER<16>.D 15.000
COUNTER<2>.Q COUNTER<6>.D 15.000
COUNTER<2>.Q COUNTER<7>.D 15.000
COUNTER<3>.Q COUNTER<10>.D 15.000
COUNTER<3>.Q COUNTER<12>.D 15.000
COUNTER<3>.Q COUNTER<14>.D 15.000
COUNTER<3>.Q COUNTER<15>.D 15.000
COUNTER<3>.Q COUNTER<16>.D 15.000
COUNTER<3>.Q COUNTER<6>.D 15.000
COUNTER<3>.Q COUNTER<7>.D 15.000
COUNTER<4>.Q COUNTER<10>.D 15.000
COUNTER<4>.Q COUNTER<12>.D 15.000
COUNTER<4>.Q COUNTER<14>.D 15.000
COUNTER<4>.Q COUNTER<15>.D 15.000
COUNTER<4>.Q COUNTER<16>.D 15.000
COUNTER<4>.Q COUNTER<6>.D 15.000
COUNTER<4>.Q COUNTER<7>.D 15.000
COUNTER<5>.Q COUNTER<10>.D 15.000
COUNTER<5>.Q COUNTER<12>.D 15.000
COUNTER<5>.Q COUNTER<14>.D 15.000
COUNTER<5>.Q COUNTER<15>.D 15.000
COUNTER<5>.Q COUNTER<16>.D 15.000
COUNTER<5>.Q COUNTER<7>.D 15.000
COUNTER<6>.Q CLK_100.D 15.000
COUNTER<6>.Q COUNTER<11>.D 15.000
COUNTER<6>.Q COUNTER<13>.D 15.000
COUNTER<6>.Q COUNTER<17>.D 15.000
COUNTER<6>.Q COUNTER<8>.D 15.000
COUNTER<6>.Q COUNTER<9>.D 15.000
COUNTER<7>.Q CLK_100.D 15.000
COUNTER<7>.Q COUNTER<11>.D 15.000
COUNTER<7>.Q COUNTER<13>.D 15.000
COUNTER<7>.Q COUNTER<17>.D 15.000
COUNTER<7>.Q COUNTER<8>.D 15.000
COUNTER<7>.Q COUNTER<9>.D 15.000
COUNTER<8>.Q COUNTER<10>.D 15.000
COUNTER<8>.Q COUNTER<12>.D 15.000
COUNTER<8>.Q COUNTER<14>.D 15.000
COUNTER<8>.Q COUNTER<15>.D 15.000
COUNTER<8>.Q COUNTER<16>.D 15.000
COUNTER<8>.Q COUNTER<7>.D 15.000
COUNTER<9>.Q COUNTER<10>.D 15.000
COUNTER<9>.Q COUNTER<12>.D 15.000
COUNTER<9>.Q COUNTER<14>.D 15.000
COUNTER<9>.Q COUNTER<15>.D 15.000
COUNTER<9>.Q COUNTER<16>.D 15.000
COUNTER<9>.Q COUNTER<7>.D 15.000
COUNTER<10>.Q COUNTER<6>.D 10.000
COUNTER<12>.Q COUNTER<6>.D 10.000
COUNTER<14>.Q COUNTER<6>.D 10.000
COUNTER<15>.Q COUNTER<6>.D 10.000
COUNTER<16>.Q COUNTER<6>.D 10.000
COUNTER<6>.Q COUNTER<6>.D 10.000
COUNTER<7>.Q COUNTER<6>.D 10.000
COUNTER<0>.Q COUNTER<1>.D 9.000
COUNTER<10>.Q COUNTER<10>.D 9.000
COUNTER<10>.Q COUNTER<12>.D 9.000
COUNTER<10>.Q COUNTER<14>.D 9.000
COUNTER<10>.Q COUNTER<15>.D 9.000
COUNTER<10>.Q COUNTER<16>.D 9.000
COUNTER<10>.Q COUNTER<7>.D 9.000
COUNTER<11>.Q CLK_100.D 9.000
COUNTER<11>.Q COUNTER<13>.D 9.000
COUNTER<11>.Q COUNTER<17>.D 9.000
COUNTER<12>.Q COUNTER<10>.D 9.000
COUNTER<12>.Q COUNTER<12>.D 9.000
COUNTER<12>.Q COUNTER<14>.D 9.000
COUNTER<12>.Q COUNTER<15>.D 9.000
COUNTER<12>.Q COUNTER<16>.D 9.000
COUNTER<12>.Q COUNTER<7>.D 9.000
COUNTER<13>.Q CLK_100.D 9.000
COUNTER<13>.Q COUNTER<17>.D 9.000
COUNTER<14>.Q COUNTER<10>.D 9.000
COUNTER<14>.Q COUNTER<12>.D 9.000
COUNTER<14>.Q COUNTER<14>.D 9.000
COUNTER<14>.Q COUNTER<15>.D 9.000
COUNTER<14>.Q COUNTER<16>.D 9.000
COUNTER<14>.Q COUNTER<7>.D 9.000
COUNTER<15>.Q COUNTER<10>.D 9.000
COUNTER<15>.Q COUNTER<12>.D 9.000
COUNTER<15>.Q COUNTER<14>.D 9.000
COUNTER<15>.Q COUNTER<15>.D 9.000
COUNTER<15>.Q COUNTER<16>.D 9.000
COUNTER<15>.Q COUNTER<7>.D 9.000
COUNTER<16>.Q COUNTER<10>.D 9.000
COUNTER<16>.Q COUNTER<12>.D 9.000
COUNTER<16>.Q COUNTER<14>.D 9.000
COUNTER<16>.Q COUNTER<15>.D 9.000
COUNTER<16>.Q COUNTER<16>.D 9.000
COUNTER<16>.Q COUNTER<7>.D 9.000
COUNTER<17>.Q CLK_100.D 9.000
COUNTER<2>.Q CLK_100.D 9.000
COUNTER<2>.Q COUNTER<11>.D 9.000
COUNTER<2>.Q COUNTER<13>.D 9.000
COUNTER<2>.Q COUNTER<17>.D 9.000
COUNTER<2>.Q COUNTER<3>.D 9.000
COUNTER<2>.Q COUNTER<4>.D 9.000
COUNTER<2>.Q COUNTER<5>.D 9.000
COUNTER<2>.Q COUNTER<8>.D 9.000
COUNTER<2>.Q COUNTER<9>.D 9.000
COUNTER<3>.Q CLK_100.D 9.000
COUNTER<3>.Q COUNTER<11>.D 9.000
COUNTER<3>.Q COUNTER<13>.D 9.000
COUNTER<3>.Q COUNTER<17>.D 9.000
COUNTER<3>.Q COUNTER<4>.D 9.000
COUNTER<3>.Q COUNTER<5>.D 9.000
COUNTER<3>.Q COUNTER<8>.D 9.000
COUNTER<3>.Q COUNTER<9>.D 9.000
COUNTER<4>.Q CLK_100.D 9.000
COUNTER<4>.Q COUNTER<11>.D 9.000
COUNTER<4>.Q COUNTER<13>.D 9.000
COUNTER<4>.Q COUNTER<17>.D 9.000
COUNTER<4>.Q COUNTER<5>.D 9.000
COUNTER<4>.Q COUNTER<8>.D 9.000
COUNTER<4>.Q COUNTER<9>.D 9.000
COUNTER<5>.Q CLK_100.D 9.000
COUNTER<5>.Q COUNTER<11>.D 9.000
COUNTER<5>.Q COUNTER<13>.D 9.000
COUNTER<5>.Q COUNTER<17>.D 9.000
COUNTER<5>.Q COUNTER<8>.D 9.000
COUNTER<5>.Q COUNTER<9>.D 9.000
COUNTER<6>.Q COUNTER<10>.D 9.000
COUNTER<6>.Q COUNTER<12>.D 9.000
COUNTER<6>.Q COUNTER<14>.D 9.000
COUNTER<6>.Q COUNTER<15>.D 9.000
COUNTER<6>.Q COUNTER<16>.D 9.000
COUNTER<6>.Q COUNTER<7>.D 9.000
COUNTER<7>.Q COUNTER<10>.D 9.000
COUNTER<7>.Q COUNTER<12>.D 9.000
COUNTER<7>.Q COUNTER<14>.D 9.000
COUNTER<7>.Q COUNTER<15>.D 9.000
COUNTER<7>.Q COUNTER<16>.D 9.000
COUNTER<7>.Q COUNTER<7>.D 9.000
COUNTER<8>.Q CLK_100.D 9.000
COUNTER<8>.Q COUNTER<11>.D 9.000
COUNTER<8>.Q COUNTER<13>.D 9.000
COUNTER<8>.Q COUNTER<17>.D 9.000
COUNTER<8>.Q COUNTER<9>.D 9.000
COUNTER<9>.Q CLK_100.D 9.000
COUNTER<9>.Q COUNTER<11>.D 9.000
COUNTER<9>.Q COUNTER<13>.D 9.000
COUNTER<9>.Q COUNTER<17>.D 9.000

Clock to Setup for clock CLK_100.Q
Source Destination Delay
MIN_L<0>.Q MIN_H<0>.D 15.000
MIN_L<0>.Q MIN_H<1>.D 15.000
MIN_L<0>.Q MIN_H<2>.D 15.000
MIN_L<0>.Q MIN_L<1>.D 15.000
MIN_L<0>.Q MIN_L<2>.D 15.000
MIN_L<1>.Q MIN_L<3>.D 15.000
MIN_L<2>.Q MIN_L<3>.D 15.000
MIN_L<3>.Q MIN_H<0>.D 15.000
MIN_L<3>.Q MIN_H<1>.D 15.000
MIN_L<3>.Q MIN_H<2>.D 15.000
MIN_L<3>.Q MIN_L<1>.D 15.000
MSEC_H<0>.Q MIN_H<0>.D 15.000
MSEC_H<0>.Q MIN_H<1>.D 15.000
MSEC_H<0>.Q MIN_H<2>.D 15.000
MSEC_H<0>.Q MIN_L<1>.D 15.000
MSEC_H<0>.Q MIN_L<2>.D 15.000
MSEC_H<0>.Q MSEC_H<1>.D 15.000
MSEC_H<0>.Q SEC_H<0>.D 15.000
MSEC_H<0>.Q SEC_H<1>.D 15.000
MSEC_H<0>.Q SEC_H<3>.D 15.000
MSEC_H<0>.Q SEC_L<1>.D 15.000
MSEC_H<0>.Q SEC_L<2>.D 15.000
MSEC_H<0>.Q SEC_L<3>.D 15.000
MSEC_H<1>.Q MIN_L<0>.D 15.000
MSEC_H<1>.Q MIN_L<3>.D 15.000
MSEC_H<1>.Q MSEC_H<2>.D 15.000
MSEC_H<1>.Q MSEC_H<3>.D 15.000
MSEC_H<1>.Q SEC_H<2>.D 15.000
MSEC_H<1>.Q SEC_L<0>.D 15.000
MSEC_H<2>.Q MIN_H<0>.D 15.000
MSEC_H<2>.Q MIN_H<1>.D 15.000
MSEC_H<2>.Q MIN_H<2>.D 15.000
MSEC_H<2>.Q MIN_L<1>.D 15.000
MSEC_H<2>.Q MIN_L<2>.D 15.000
MSEC_H<2>.Q MSEC_H<1>.D 15.000
MSEC_H<2>.Q SEC_H<0>.D 15.000
MSEC_H<2>.Q SEC_H<1>.D 15.000
MSEC_H<2>.Q SEC_H<3>.D 15.000
MSEC_H<2>.Q SEC_L<1>.D 15.000
MSEC_H<2>.Q SEC_L<2>.D 15.000
MSEC_H<2>.Q SEC_L<3>.D 15.000
MSEC_H<3>.Q MIN_H<0>.D 15.000
MSEC_H<3>.Q MIN_H<1>.D 15.000
MSEC_H<3>.Q MIN_H<2>.D 15.000
MSEC_H<3>.Q MIN_L<1>.D 15.000
MSEC_H<3>.Q MIN_L<2>.D 15.000
MSEC_H<3>.Q MSEC_H<1>.D 15.000
MSEC_H<3>.Q SEC_H<0>.D 15.000
MSEC_H<3>.Q SEC_H<1>.D 15.000
MSEC_H<3>.Q SEC_H<3>.D 15.000
MSEC_H<3>.Q SEC_L<1>.D 15.000
MSEC_H<3>.Q SEC_L<2>.D 15.000
MSEC_H<3>.Q SEC_L<3>.D 15.000
MSEC_L<0>.Q MIN_H<0>.D 15.000
MSEC_L<0>.Q MIN_H<1>.D 15.000
MSEC_L<0>.Q MIN_H<2>.D 15.000
MSEC_L<0>.Q MIN_L<0>.D 15.000
MSEC_L<0>.Q MIN_L<1>.D 15.000
MSEC_L<0>.Q MIN_L<2>.D 15.000
MSEC_L<0>.Q MIN_L<3>.D 15.000
MSEC_L<0>.Q MSEC_H<0>.D 15.000
MSEC_L<0>.Q MSEC_H<1>.D 15.000
MSEC_L<0>.Q MSEC_H<2>.D 15.000
MSEC_L<0>.Q MSEC_H<3>.D 15.000
MSEC_L<0>.Q MSEC_L<1>.D 15.000
MSEC_L<0>.Q MSEC_L<2>.D 15.000
MSEC_L<0>.Q MSEC_L<3>.D 15.000
MSEC_L<0>.Q SEC_H<0>.D 15.000
MSEC_L<0>.Q SEC_H<1>.D 15.000
MSEC_L<0>.Q SEC_H<2>.D 15.000
MSEC_L<0>.Q SEC_H<3>.D 15.000
MSEC_L<0>.Q SEC_L<0>.D 15.000
MSEC_L<0>.Q SEC_L<1>.D 15.000
MSEC_L<0>.Q SEC_L<2>.D 15.000
MSEC_L<0>.Q SEC_L<3>.D 15.000
MSEC_L<1>.Q MIN_H<0>.D 15.000
MSEC_L<1>.Q MIN_H<1>.D 15.000
MSEC_L<1>.Q MIN_H<2>.D 15.000
MSEC_L<1>.Q MIN_L<1>.D 15.000
MSEC_L<1>.Q MIN_L<2>.D 15.000
MSEC_L<1>.Q MSEC_H<1>.D 15.000
MSEC_L<1>.Q SEC_H<0>.D 15.000
MSEC_L<1>.Q SEC_H<1>.D 15.000
MSEC_L<1>.Q SEC_H<3>.D 15.000
MSEC_L<1>.Q SEC_L<1>.D 15.000
MSEC_L<1>.Q SEC_L<2>.D 15.000
MSEC_L<1>.Q SEC_L<3>.D 15.000
MSEC_L<2>.Q MIN_H<0>.D 15.000
MSEC_L<2>.Q MIN_H<1>.D 15.000
MSEC_L<2>.Q MIN_H<2>.D 15.000
MSEC_L<2>.Q MIN_L<1>.D 15.000
MSEC_L<2>.Q MIN_L<2>.D 15.000
MSEC_L<2>.Q MSEC_H<1>.D 15.000
MSEC_L<2>.Q SEC_H<0>.D 15.000
MSEC_L<2>.Q SEC_H<1>.D 15.000
MSEC_L<2>.Q SEC_H<3>.D 15.000
MSEC_L<2>.Q SEC_L<1>.D 15.000
MSEC_L<2>.Q SEC_L<2>.D 15.000
MSEC_L<2>.Q SEC_L<3>.D 15.000
MSEC_L<3>.Q MIN_H<0>.D 15.000
MSEC_L<3>.Q MIN_H<1>.D 15.000
MSEC_L<3>.Q MIN_H<2>.D 15.000
MSEC_L<3>.Q MIN_L<1>.D 15.000
MSEC_L<3>.Q MIN_L<2>.D 15.000
MSEC_L<3>.Q MSEC_H<1>.D 15.000
MSEC_L<3>.Q SEC_H<0>.D 15.000
MSEC_L<3>.Q SEC_H<1>.D 15.000
MSEC_L<3>.Q SEC_H<3>.D 15.000
MSEC_L<3>.Q SEC_L<1>.D 15.000
MSEC_L<3>.Q SEC_L<2>.D 15.000
MSEC_L<3>.Q SEC_L<3>.D 15.000
SEC_H<0>.Q MIN_L<0>.D 15.000
SEC_H<0>.Q MIN_L<3>.D 15.000
SEC_H<0>.Q SEC_H<2>.D 15.000
SEC_H<1>.Q MIN_L<0>.D 15.000
SEC_H<1>.Q MIN_L<3>.D 15.000
SEC_H<1>.Q SEC_H<2>.D 15.000
SEC_H<2>.Q MIN_H<0>.D 15.000
SEC_H<2>.Q MIN_H<1>.D 15.000
SEC_H<2>.Q MIN_H<2>.D 15.000
SEC_H<2>.Q MIN_L<1>.D 15.000
SEC_H<2>.Q MIN_L<2>.D 15.000
SEC_H<2>.Q SEC_H<1>.D 15.000
SEC_H<2>.Q SEC_H<3>.D 15.000
SEC_H<3>.Q MIN_L<0>.D 15.000
SEC_H<3>.Q MIN_L<3>.D 15.000
SEC_H<3>.Q SEC_H<2>.D 15.000
SEC_L<0>.Q MIN_H<0>.D 15.000
SEC_L<0>.Q MIN_H<1>.D 15.000
SEC_L<0>.Q MIN_H<2>.D 15.000
SEC_L<0>.Q MIN_L<1>.D 15.000
SEC_L<0>.Q MIN_L<2>.D 15.000
SEC_L<0>.Q SEC_H<0>.D 15.000
SEC_L<0>.Q SEC_H<1>.D 15.000
SEC_L<0>.Q SEC_H<3>.D 15.000
SEC_L<0>.Q SEC_L<1>.D 15.000
SEC_L<0>.Q SEC_L<2>.D 15.000
SEC_L<0>.Q SEC_L<3>.D 15.000
SEC_L<1>.Q MIN_L<0>.D 15.000
SEC_L<1>.Q MIN_L<3>.D 15.000
SEC_L<1>.Q SEC_H<2>.D 15.000
SEC_L<2>.Q MIN_L<0>.D 15.000
SEC_L<2>.Q MIN_L<3>.D 15.000
SEC_L<2>.Q SEC_H<2>.D 15.000
SEC_L<3>.Q MIN_L<0>.D 15.000
SEC_L<3>.Q MIN_L<3>.D 15.000
SEC_L<3>.Q SEC_H<2>.D 15.000
MIN_H<0>.Q MIN_H<0>.D 9.000
MIN_H<0>.Q MIN_H<1>.D 9.000
MIN_H<0>.Q MIN_H<2>.D 9.000
MIN_H<1>.Q MIN_H<0>.D 9.000
MIN_H<1>.Q MIN_H<1>.D 9.000
MIN_H<1>.Q MIN_H<2>.D 9.000
MIN_H<2>.Q MIN_H<0>.D 9.000
MIN_H<2>.Q MIN_H<1>.D 9.000
MIN_H<2>.Q MIN_H<2>.D 9.000
MIN_L<0>.Q MIN_L<3>.D 9.000
MIN_L<1>.Q MIN_H<0>.D 9.000
MIN_L<1>.Q MIN_H<1>.D 9.000
MIN_L<1>.Q MIN_H<2>.D 9.000
MIN_L<1>.Q MIN_L<1>.D 9.000
MIN_L<1>.Q MIN_L<2>.D 9.000
MIN_L<2>.Q MIN_H<0>.D 9.000
MIN_L<2>.Q MIN_H<1>.D 9.000
MIN_L<2>.Q MIN_H<2>.D 9.000
MIN_L<2>.Q MIN_L<1>.D 9.000
MIN_L<3>.Q MIN_L<3>.D 9.000
MSEC_H<0>.Q MIN_L<0>.D 9.000
MSEC_H<0>.Q MIN_L<3>.D 9.000
MSEC_H<0>.Q MSEC_H<2>.D 9.000
MSEC_H<0>.Q MSEC_H<3>.D 9.000
MSEC_H<0>.Q SEC_H<2>.D 9.000
MSEC_H<0>.Q SEC_L<0>.D 9.000
MSEC_H<1>.Q MIN_H<0>.D 9.000
MSEC_H<1>.Q MIN_H<1>.D 9.000
MSEC_H<1>.Q MIN_H<2>.D 9.000
MSEC_H<1>.Q MIN_L<1>.D 9.000
MSEC_H<1>.Q MIN_L<2>.D 9.000
MSEC_H<1>.Q MSEC_H<1>.D 9.000
MSEC_H<1>.Q SEC_H<0>.D 9.000
MSEC_H<1>.Q SEC_H<1>.D 9.000
MSEC_H<1>.Q SEC_H<3>.D 9.000
MSEC_H<1>.Q SEC_L<1>.D 9.000
MSEC_H<1>.Q SEC_L<2>.D 9.000
MSEC_H<1>.Q SEC_L<3>.D 9.000
MSEC_H<2>.Q MIN_L<0>.D 9.000
MSEC_H<2>.Q MIN_L<3>.D 9.000
MSEC_H<2>.Q MSEC_H<3>.D 9.000
MSEC_H<2>.Q SEC_H<2>.D 9.000
MSEC_H<2>.Q SEC_L<0>.D 9.000
MSEC_H<3>.Q MIN_L<0>.D 9.000
MSEC_H<3>.Q MIN_L<3>.D 9.000
MSEC_H<3>.Q MSEC_H<3>.D 9.000
MSEC_H<3>.Q SEC_H<2>.D 9.000
MSEC_H<3>.Q SEC_L<0>.D 9.000
MSEC_L<1>.Q MIN_L<0>.D 9.000
MSEC_L<1>.Q MIN_L<3>.D 9.000
MSEC_L<1>.Q MSEC_H<0>.D 9.000
MSEC_L<1>.Q MSEC_H<2>.D 9.000
MSEC_L<1>.Q MSEC_H<3>.D 9.000
MSEC_L<1>.Q MSEC_L<1>.D 9.000
MSEC_L<1>.Q MSEC_L<2>.D 9.000
MSEC_L<1>.Q MSEC_L<3>.D 9.000
MSEC_L<1>.Q SEC_H<2>.D 9.000
MSEC_L<1>.Q SEC_L<0>.D 9.000
MSEC_L<2>.Q MIN_L<0>.D 9.000
MSEC_L<2>.Q MIN_L<3>.D 9.000
MSEC_L<2>.Q MSEC_H<0>.D 9.000
MSEC_L<2>.Q MSEC_H<2>.D 9.000
MSEC_L<2>.Q MSEC_H<3>.D 9.000
MSEC_L<2>.Q MSEC_L<1>.D 9.000
MSEC_L<2>.Q MSEC_L<3>.D 9.000
MSEC_L<2>.Q SEC_H<2>.D 9.000
MSEC_L<2>.Q SEC_L<0>.D 9.000
MSEC_L<3>.Q MIN_L<0>.D 9.000
MSEC_L<3>.Q MIN_L<3>.D 9.000
MSEC_L<3>.Q MSEC_H<0>.D 9.000
MSEC_L<3>.Q MSEC_H<2>.D 9.000
MSEC_L<3>.Q MSEC_H<3>.D 9.000
MSEC_L<3>.Q MSEC_L<1>.D 9.000
MSEC_L<3>.Q MSEC_L<3>.D 9.000
MSEC_L<3>.Q SEC_H<2>.D 9.000
MSEC_L<3>.Q SEC_L<0>.D 9.000
SEC_H<0>.Q MIN_H<0>.D 9.000
SEC_H<0>.Q MIN_H<1>.D 9.000
SEC_H<0>.Q MIN_H<2>.D 9.000
SEC_H<0>.Q MIN_L<1>.D 9.000
SEC_H<0>.Q MIN_L<2>.D 9.000
SEC_H<0>.Q SEC_H<1>.D 9.000
SEC_H<0>.Q SEC_H<3>.D 9.000
SEC_H<1>.Q MIN_H<0>.D 9.000
SEC_H<1>.Q MIN_H<1>.D 9.000
SEC_H<1>.Q MIN_H<2>.D 9.000
SEC_H<1>.Q MIN_L<1>.D 9.000
SEC_H<1>.Q MIN_L<2>.D 9.000
SEC_H<1>.Q SEC_H<1>.D 9.000
SEC_H<1>.Q SEC_H<3>.D 9.000
SEC_H<2>.Q MIN_L<0>.D 9.000
SEC_H<2>.Q MIN_L<3>.D 9.000
SEC_H<2>.Q SEC_H<2>.D 9.000
SEC_H<3>.Q MIN_H<0>.D 9.000
SEC_H<3>.Q MIN_H<1>.D 9.000
SEC_H<3>.Q MIN_H<2>.D 9.000
SEC_H<3>.Q MIN_L<1>.D 9.000
SEC_H<3>.Q MIN_L<2>.D 9.000
SEC_H<3>.Q SEC_H<1>.D 9.000
SEC_L<0>.Q MIN_L<0>.D 9.000
SEC_L<0>.Q MIN_L<3>.D 9.000
SEC_L<0>.Q SEC_H<2>.D 9.000
SEC_L<1>.Q MIN_H<0>.D 9.000
SEC_L<1>.Q MIN_H<1>.D 9.000
SEC_L<1>.Q MIN_H<2>.D 9.000
SEC_L<1>.Q MIN_L<1>.D 9.000
SEC_L<1>.Q MIN_L<2>.D 9.000
SEC_L<1>.Q SEC_H<0>.D 9.000
SEC_L<1>.Q SEC_H<1>.D 9.000
SEC_L<1>.Q SEC_H<3>.D 9.000
SEC_L<1>.Q SEC_L<1>.D 9.000
SEC_L<1>.Q SEC_L<2>.D 9.000
SEC_L<1>.Q SEC_L<3>.D 9.000
SEC_L<2>.Q MIN_H<0>.D 9.000
SEC_L<2>.Q MIN_H<1>.D 9.000
SEC_L<2>.Q MIN_H<2>.D 9.000
SEC_L<2>.Q MIN_L<1>.D 9.000
SEC_L<2>.Q MIN_L<2>.D 9.000
SEC_L<2>.Q SEC_H<0>.D 9.000
SEC_L<2>.Q SEC_H<1>.D 9.000
SEC_L<2>.Q SEC_H<3>.D 9.000
SEC_L<2>.Q SEC_L<1>.D 9.000
SEC_L<2>.Q SEC_L<3>.D 9.000
SEC_L<3>.Q MIN_H<0>.D 9.000
SEC_L<3>.Q MIN_H<1>.D 9.000
SEC_L<3>.Q MIN_H<2>.D 9.000
SEC_L<3>.Q MIN_L<1>.D 9.000
SEC_L<3>.Q MIN_L<2>.D 9.000
SEC_L<3>.Q SEC_H<0>.D 9.000
SEC_L<3>.Q SEC_H<1>.D 9.000
SEC_L<3>.Q SEC_H<3>.D 9.000
SEC_L<3>.Q SEC_L<1>.D 9.000
SEC_L<3>.Q SEC_L<3>.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 521
Number of Timing errors: 521
Analysis Completed: Fri Apr 23 20:21:44 2010