cpldfit:  version J.30                              Xilinx Inc.
                                  Fitter Report
Design Name: FREQUENCY                           Date:  4-30-2010,  3:29PM
Device Used: XC95108-10-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
74 /108 ( 69%) 210 /540  ( 39%) 129/216 ( 60%)   60 /108 ( 56%) 14 /69  ( 20%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          16/18       26/36       26          40/90       0/12
FB2          13/18       31/36       31          43/90       2/12
FB3          13/18       16/36       16          12/90       0/12
FB4          16/18       31/36       31          81/90       7/11
FB5           0/18        0/36        0           0/90       0/11
FB6          16/18       25/36       25          34/90       3/11
             -----       -----                   -----       -----     
             74/108     129/216                 210/540     12/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
Signal 'FX' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    0           0    |  I/O              :    12      63
Output        :   12          12    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    2           2    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     14          14

** Power Data **

There are 74 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB4,
   because too many function block product terms are required. Buffering output
   signal SEG<5> to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 12 Outputs **

Signal                              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                Pts   Inps          No.  Type    Use     Mode Rate State
SEG<1>                              10    20    FB2_2   71   I/O     O       STD  FAST 
SEG<0>                              10    20    FB2_3   72   I/O     O       STD  FAST 
SEL<3>                              1     2     FB4_2   57   I/O     O       STD  FAST 
SEG<7>                              1     1     FB4_9   65   I/O     O       STD  FAST 
SEG<6>                              9     20    FB4_11  66   I/O     O       STD  FAST 
SEG<5>                              2     2     FB4_12  67   I/O     O       STD  FAST 
SEG<4>                              9     20    FB4_14  68   I/O     O       STD  FAST 
SEG<3>                              14    20    FB4_15  69   I/O     O       STD  FAST 
SEG<2>                              6     20    FB4_17  70   I/O     O       STD  FAST 
SEL<0>                              1     2     FB6_14  54   I/O     O       STD  FAST 
SEL<1>                              1     2     FB6_15  55   I/O     O       STD  FAST 
SEL<2>                              1     2     FB6_17  56   I/O     O       STD  FAST 

** 62 Buried Nodes **

Signal                              Total Total Loc     Pwr  Reg Init
Name                                Pts   Inps          Mode State
DISP_CNT<9>                         2     4     FB1_3   STD  RESET
DISP_CNT<15>                        2     4     FB1_4   STD  RESET
DISP_CNT<14>                        2     4     FB1_5   STD  RESET
DISP_CNT<13>                        2     4     FB1_6   STD  RESET
DISP_CNT<12>                        2     4     FB1_7   STD  RESET
DISP_CNT<11>                        2     4     FB1_8   STD  RESET
DISP_CNT<10>                        2     4     FB1_9   STD  RESET
CNT<2>                              2     5     FB1_10  STD  RESET
CNT<15>                             2     18    FB1_11  STD  RESET
CNT<14>                             2     17    FB1_12  STD  RESET
CNT<13>                             2     16    FB1_13  STD  RESET
CNT<12>                             2     15    FB1_14  STD  RESET
CNT<10>                             2     13    FB1_15  STD  RESET
CNT<11>                             3     14    FB1_16  STD  RESET
CNT<9>                              4     14    FB1_17  STD  RESET
OVER_FLAG                           7     18    FB1_18  STD  RESET
DISP_CNT<8>                         2     4     FB2_8   STD  RESET
DISP_CNT<7>                         2     4     FB2_9   STD  RESET
DISP_CNT<6>                         2     4     FB2_10  STD  RESET
DISP_CNT<5>                         2     4     FB2_11  STD  RESET
DISP_CNT<4>                         2     4     FB2_12  STD  RESET
DISP_CNT<3>                         2     4     FB2_13  STD  RESET
DISP_CNT<2>                         2     4     FB2_14  STD  RESET
DISP_CNT<1>                         2     4     FB2_15  STD  RESET
CNT<8>                              2     11    FB2_16  STD  RESET
CNT<0>                              2     3     FB2_17  STD  RESET
CNT<3>                              3     6     FB2_18  STD  RESET
COUNTER<8>                          1     8     FB3_6   STD  RESET
COUNTER<7>                          1     7     FB3_7   STD  RESET
COUNTER<6>                          1     6     FB3_8   STD  RESET
COUNTER<5>                          1     5     FB3_9   STD  RESET
COUNTER<4>                          1     4     FB3_10  STD  RESET
COUNTER<3>                          1     3     FB3_11  STD  RESET
COUNTER<2>                          1     2     FB3_12  STD  RESET
COUNTER<1>                          1     1     FB3_13  STD  RESET
COUNTER<16>                         1     16    FB3_14  STD  RESET
COUNTER<15>                         1     15    FB3_15  STD  RESET
COUNTER<14>                         1     14    FB3_16  STD  RESET
COUNTER<11>                         1     11    FB3_17  STD  RESET
COUNTER<0>                          0     0     FB3_18  STD  RESET

Signal                              Total Total Loc     Pwr  Reg Init
Name                                Pts   Inps          Mode State
DISP_CNT<0>                         2     4     FB4_3   STD  RESET
CNT<6>                              2     9     FB4_4   STD  RESET
CNT<4>                              2     7     FB4_5   STD  RESET
CNT<7>                              3     10    FB4_6   STD  RESET
CNT<5>                              4     10    FB4_7   STD  RESET
SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT  8     15    FB4_8   STD  
CNT<1>                              4     6     FB4_10  STD  RESET
DATA_FLAG                           1     1     FB4_16  STD  RESET
SEG<5>_BUFR                         13    19    FB4_18  STD  
SEC_FLAG                            1     25    FB6_3   STD  RESET
COUNTER<23>                         1     23    FB6_4   STD  RESET
COUNTER<20>                         1     20    FB6_5   STD  RESET
COUNTER<24>                         2     25    FB6_6   STD  RESET
COUNTER<22>                         2     25    FB6_7   STD  RESET
COUNTER<21>                         2     25    FB6_8   STD  RESET
COUNTER<19>                         2     25    FB6_9   STD  RESET
COUNTER<18>                         2     25    FB6_10  STD  RESET
COUNTER<17>                         2     25    FB6_11  STD  RESET
COUNTER<13>                         2     25    FB6_12  STD  RESET
COUNTER<12>                         2     25    FB6_13  STD  RESET
COUNTER<10>                         2     25    FB6_16  STD  RESET
COUNTER<9>                          10    25    FB6_18  STD  RESET

** 2 Inputs **

Signal                              Loc     Pin  Pin     Pin     
Name                                        No.  Type    Use     
CLK                                 FB1_12  9    GCK/I/O GCK
FX                                  FB1_14  10   GCK/I/O GCK

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               26/10
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB1_1         (b)     (b)
(unused)              0       0     0   5     FB1_2   1     I/O     
DISP_CNT<9>           2       0     0   3     FB1_3   2     I/O     (b)
DISP_CNT<15>          2       0     0   3     FB1_4         (b)     (b)
DISP_CNT<14>          2       0     0   3     FB1_5   3     I/O     (b)
DISP_CNT<13>          2       0     0   3     FB1_6   4     I/O     (b)
DISP_CNT<12>          2       0     0   3     FB1_7         (b)     (b)
DISP_CNT<11>          2       0     0   3     FB1_8   5     I/O     (b)
DISP_CNT<10>          2       0     0   3     FB1_9   6     I/O     (b)
CNT<2>                2       0     0   3     FB1_10        (b)     (b)
CNT<15>               2       0     0   3     FB1_11  7     I/O     (b)
CNT<14>               2       0     0   3     FB1_12  9     GCK/I/O GCK
CNT<13>               2       0     0   3     FB1_13        (b)     (b)
CNT<12>               2       0     0   3     FB1_14  10    GCK/I/O GCK
CNT<10>               2       0     0   3     FB1_15  11    I/O     (b)
CNT<11>               3       0     0   2     FB1_16  12    GCK/I/O (b)
CNT<9>                4       0   \/1   0     FB1_17  13    I/O     (b)
OVER_FLAG             7       2<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CNT<0>            10: CNT<3>             19: DISP_CNT<11>.LFBK 
  2: CNT<10>.LFBK      11: CNT<4>             20: DISP_CNT<12>.LFBK 
  3: CNT<11>.LFBK      12: CNT<5>             21: DISP_CNT<13>.LFBK 
  4: CNT<12>.LFBK      13: CNT<6>             22: DISP_CNT<14>.LFBK 
  5: CNT<13>.LFBK      14: CNT<7>             23: DISP_CNT<15>.LFBK 
  6: CNT<14>.LFBK      15: CNT<8>             24: DISP_CNT<9>.LFBK 
  7: CNT<15>.LFBK      16: CNT<9>.LFBK        25: OVER_FLAG.LFBK 
  8: CNT<1>            17: DATA_FLAG          26: SEC_FLAG 
  9: CNT<2>.LFBK       18: DISP_CNT<10>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
DISP_CNT<9>          ...............XX......X.X.............. 4       4
DISP_CNT<15>         ......X.........X.....X..X.............. 4       4
DISP_CNT<14>         .....X..........X....X...X.............. 4       4
DISP_CNT<13>         ....X...........X...X....X.............. 4       4
DISP_CNT<12>         ...X............X..X.....X.............. 4       4
DISP_CNT<11>         ..X.............X.X......X.............. 4       4
DISP_CNT<10>         .X..............XX.......X.............. 4       4
CNT<2>               X......XX.......X........X.............. 5       5
CNT<15>              XXXXXXXXXXXXXXXXX........X.............. 18      18
CNT<14>              XXXXXX.XXXXXXXXXX........X.............. 17      17
CNT<13>              XXXXX..XXXXXXXXXX........X.............. 16      16
CNT<12>              XXXX...XXXXXXXXXX........X.............. 15      15
CNT<10>              XX.....XXXXXXXXXX........X.............. 13      13
CNT<11>              XXX....XXXXXXXXXX........X.............. 14      14
CNT<9>               XXX....XXXXXXXXXX........X.............. 14      14
OVER_FLAG            XXXXXXXXXXXXXXXX........XX.............. 18      18
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB2_1         (b)     (b)
SEG<1>               10       5<-   0   0     FB2_2   71    I/O     O
SEG<0>               10       5<-   0   0     FB2_3   72    I/O     O
(unused)              0       0   /\5   0     FB2_4         (b)     (b)
(unused)              0       0     0   5     FB2_5   74    GSR/I/O 
(unused)              0       0     0   5     FB2_6   75    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
DISP_CNT<8>           2       0     0   3     FB2_8   76    GTS/I/O (b)
DISP_CNT<7>           2       0     0   3     FB2_9   77    GTS/I/O (b)
DISP_CNT<6>           2       0     0   3     FB2_10        (b)     (b)
DISP_CNT<5>           2       0     0   3     FB2_11  79    I/O     (b)
DISP_CNT<4>           2       0     0   3     FB2_12  80    I/O     (b)
DISP_CNT<3>           2       0     0   3     FB2_13        (b)     (b)
DISP_CNT<2>           2       0     0   3     FB2_14  81    I/O     (b)
DISP_CNT<1>           2       0     0   3     FB2_15  82    I/O     (b)
CNT<8>                2       0     0   3     FB2_16  83    I/O     (b)
CNT<0>                2       0     0   3     FB2_17  84    I/O     (b)
CNT<3>                3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CNT<0>.LFBK       12: DATA_FLAG         22: DISP_CNT<3>.LFBK 
  2: CNT<1>            13: DISP_CNT<0>       23: DISP_CNT<4>.LFBK 
  3: CNT<2>            14: DISP_CNT<10>      24: DISP_CNT<5>.LFBK 
  4: CNT<3>.LFBK       15: DISP_CNT<11>      25: DISP_CNT<6>.LFBK 
  5: CNT<4>            16: DISP_CNT<12>      26: DISP_CNT<7>.LFBK 
  6: CNT<5>            17: DISP_CNT<13>      27: DISP_CNT<8>.LFBK 
  7: CNT<6>            18: DISP_CNT<14>      28: DISP_CNT<9> 
  8: CNT<7>            19: DISP_CNT<15>      29: OVER_FLAG 
  9: CNT<8>.LFBK       20: DISP_CNT<1>.LFBK  30: SEC_FLAG 
 10: COUNTER<11>       21: DISP_CNT<2>.LFBK  31: SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT 
 11: COUNTER<12>      

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEG<1>               .........XX.XXXXXXXXXXXXXXXXX.X......... 20      20
SEG<0>               .........XX.XXXXXXXXXXXXXXXXX.X......... 20      20
DISP_CNT<8>          ........X..X..............X..X.......... 4       4
DISP_CNT<7>          .......X...X.............X...X.......... 4       4
DISP_CNT<6>          ......X....X............X....X.......... 4       4
DISP_CNT<5>          .....X.....X...........X.....X.......... 4       4
DISP_CNT<4>          ....X......X..........X......X.......... 4       4
DISP_CNT<3>          ...X.......X.........X.......X.......... 4       4
DISP_CNT<2>          ..X........X........X........X.......... 4       4
DISP_CNT<1>          .X.........X.......X.........X.......... 4       4
CNT<8>               XXXXXXXXX..X.................X.......... 11      11
CNT<0>               X..........X.................X.......... 3       3
CNT<3>               XXXX.......X.................X.......... 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               16/20
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   14    I/O     
(unused)              0       0     0   5     FB3_3   15    I/O     
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   17    I/O     
COUNTER<8>            1       0     0   4     FB3_6   18    I/O     (b)
COUNTER<7>            1       0     0   4     FB3_7         (b)     (b)
COUNTER<6>            1       0     0   4     FB3_8   19    I/O     (b)
COUNTER<5>            1       0     0   4     FB3_9   20    I/O     (b)
COUNTER<4>            1       0     0   4     FB3_10        (b)     (b)
COUNTER<3>            1       0     0   4     FB3_11  21    I/O     (b)
COUNTER<2>            1       0     0   4     FB3_12  23    I/O     (b)
COUNTER<1>            1       0     0   4     FB3_13        (b)     (b)
COUNTER<16>           1       0     0   4     FB3_14  24    I/O     (b)
COUNTER<15>           1       0     0   4     FB3_15  25    I/O     (b)
COUNTER<14>           1       0     0   4     FB3_16  26    I/O     (b)
COUNTER<11>           1       0     0   4     FB3_17  31    I/O     (b)
COUNTER<0>            0       0     0   5     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: COUNTER<0>.LFBK    7: COUNTER<15>.LFBK  12: COUNTER<5>.LFBK 
  2: COUNTER<10>        8: COUNTER<1>.LFBK   13: COUNTER<6>.LFBK 
  3: COUNTER<11>.LFBK   9: COUNTER<2>.LFBK   14: COUNTER<7>.LFBK 
  4: COUNTER<12>       10: COUNTER<3>.LFBK   15: COUNTER<8>.LFBK 
  5: COUNTER<13>       11: COUNTER<4>.LFBK   16: COUNTER<9> 
  6: COUNTER<14>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
COUNTER<8>           X......XXXXXXX.......................... 8       8
COUNTER<7>           X......XXXXXX........................... 7       7
COUNTER<6>           X......XXXXX............................ 6       6
COUNTER<5>           X......XXXX............................. 5       5
COUNTER<4>           X......XXX.............................. 4       4
COUNTER<3>           X......XX............................... 3       3
COUNTER<2>           X......X................................ 2       2
COUNTER<1>           X....................................... 1       1
COUNTER<16>          XXXXXXXXXXXXXXXX........................ 16      16
COUNTER<15>          XXXXXX.XXXXXXXXX........................ 15      15
COUNTER<14>          XXXXX..XXXXXXXXX........................ 14      14
COUNTER<11>          XX.....XXXXXXXXX........................ 11      11
COUNTER<0>           ........................................ 0       0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB4_1         (b)     (b)
SEL<3>                1       1<- /\5   0     FB4_2   57    I/O     O
DISP_CNT<0>           2       0   /\1   2     FB4_3   58    I/O     (b)
CNT<6>                2       0     0   3     FB4_4         (b)     (b)
CNT<4>                2       0     0   3     FB4_5   61    I/O     (b)
CNT<7>                3       0   \/2   0     FB4_6   62    I/O     (b)
CNT<5>                4       2<- \/3   0     FB4_7         (b)     (b)
SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT
                      8       3<-   0   0     FB4_8   63    I/O     (b)
SEG<7>                1       0   \/3   1     FB4_9   65    I/O     O
CNT<1>                4       3<- \/4   0     FB4_10        (b)     (b)
SEG<6>                9       4<-   0   0     FB4_11  66    I/O     O
SEG<5>                2       0   \/3   0     FB4_12  67    I/O     O
(unused)              0       0   \/5   0     FB4_13        (b)     (b)
SEG<4>                9       8<- \/4   0     FB4_14  68    I/O     O
SEG<3>               14       9<-   0   0     FB4_15  69    I/O     O
DATA_FLAG             1       1<- /\5   0     FB4_16        (b)     (b)
SEG<2>                6       2<- /\1   0     FB4_17  70    I/O     O
SEG<5>_BUFR          13      10<- /\2   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CNT<0>            12: DISP_CNT<0>.LFBK  22: DISP_CNT<4> 
  2: CNT<1>.LFBK       13: DISP_CNT<10>      23: DISP_CNT<5> 
  3: CNT<2>            14: DISP_CNT<11>      24: DISP_CNT<6> 
  4: CNT<3>            15: DISP_CNT<12>      25: DISP_CNT<7> 
  5: CNT<4>.LFBK       16: DISP_CNT<13>      26: DISP_CNT<8> 
  6: CNT<5>.LFBK       17: DISP_CNT<14>      27: DISP_CNT<9> 
  7: CNT<6>.LFBK       18: DISP_CNT<15>      28: OVER_FLAG 
  8: CNT<7>.LFBK       19: DISP_CNT<1>       29: SEC_FLAG 
  9: COUNTER<11>       20: DISP_CNT<2>       30: SEG<5>_BUFR.LFBK 
 10: COUNTER<12>       21: DISP_CNT<3>       31: SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK 
 11: DATA_FLAG.LFBK   

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEL<3>               ........XX.............................. 2       2
DISP_CNT<0>          X.........XX................X........... 4       4
CNT<6>               XXXXXXX...X.................X........... 9       9
CNT<4>               XXXXX.....X.................X........... 7       7
CNT<7>               XXXXXXXX..X.................X........... 10      10
CNT<5>               XXXXXXXX..X.................X........... 10      10
SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT 
                     ........XX..XX.XXXXXX.XXX.XX............ 15      15
SEG<7>               ..............................X......... 1       1
CNT<1>               XXXX......X.................X........... 6       6
SEG<6>               ........XX.XXXXXXXXXXXXXXXXX..X......... 20      20
SEG<5>               .............................XX......... 2       2
SEG<4>               ........XX.XXXXXXXXXXXXXXXXX..X......... 20      20
SEG<3>               ........XX.XXXXXXXXXXXXXXXXX..X......... 20      20
DATA_FLAG            ............................X........... 1       1
SEG<2>               ........XX.XXXXXXXXXXXXXXXXX..X......... 20      20
SEG<5>_BUFR          ........XX.XXXXXXXXXXXXXXXXX............ 19      19
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   32    I/O     
(unused)              0       0     0   5     FB5_3   33    I/O     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   34    I/O     
(unused)              0       0     0   5     FB5_6   35    I/O     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   36    I/O     
(unused)              0       0     0   5     FB5_9   37    I/O     
(unused)              0       0     0   5     FB5_10        (b)     
(unused)              0       0     0   5     FB5_11  39    I/O     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               25/11
Number of signals used by logic mapping into function block:  25
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\1   4     FB6_1         (b)     (b)
(unused)              0       0     0   5     FB6_2   45    I/O     
SEC_FLAG              1       0     0   4     FB6_3   46    I/O     (b)
COUNTER<23>           1       0     0   4     FB6_4         (b)     (b)
COUNTER<20>           1       0     0   4     FB6_5   47    I/O     (b)
COUNTER<24>           2       0     0   3     FB6_6   48    I/O     (b)
COUNTER<22>           2       0     0   3     FB6_7         (b)     (b)
COUNTER<21>           2       0     0   3     FB6_8   50    I/O     (b)
COUNTER<19>           2       0     0   3     FB6_9   51    I/O     (b)
COUNTER<18>           2       0     0   3     FB6_10        (b)     (b)
COUNTER<17>           2       0     0   3     FB6_11  52    I/O     (b)
COUNTER<13>           2       0     0   3     FB6_12  53    I/O     (b)
COUNTER<12>           2       0     0   3     FB6_13        (b)     (b)
SEL<0>                1       0     0   4     FB6_14  54    I/O     O
SEL<1>                1       0     0   4     FB6_15  55    I/O     O
COUNTER<10>           2       0     0   3     FB6_16        (b)     (b)
SEL<2>                1       0   \/4   0     FB6_17  56    I/O     O
COUNTER<9>           10       5<-   0   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: COUNTER<0>        10: COUNTER<18>.LFBK  18: COUNTER<2> 
  2: COUNTER<10>.LFBK  11: COUNTER<19>.LFBK  19: COUNTER<3> 
  3: COUNTER<11>       12: COUNTER<1>        20: COUNTER<4> 
  4: COUNTER<12>.LFBK  13: COUNTER<20>.LFBK  21: COUNTER<5> 
  5: COUNTER<13>.LFBK  14: COUNTER<21>.LFBK  22: COUNTER<6> 
  6: COUNTER<14>       15: COUNTER<22>.LFBK  23: COUNTER<7> 
  7: COUNTER<15>       16: COUNTER<23>.LFBK  24: COUNTER<8> 
  8: COUNTER<16>       17: COUNTER<24>.LFBK  25: COUNTER<9>.LFBK 
  9: COUNTER<17>.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
SEC_FLAG             XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<23>          XXXXXXXXXXXXXXX..XXXXXXXX............... 23      23
COUNTER<20>          XXXXXXXXXXXX.....XXXXXXXX............... 20      20
COUNTER<24>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<22>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<21>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<19>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<18>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<17>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<13>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
COUNTER<12>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
SEL<0>               ..XX.................................... 2       2
SEL<1>               ..XX.................................... 2       2
COUNTER<10>          XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
SEL<2>               ..XX.................................... 2       2
COUNTER<9>           XXXXXXXXXXXXXXXXXXXXXXXXX............... 25      25
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_CNT0: FDCPE port map (CNT(0),CNT_D(0),FX,'0','0');
CNT_D(0) <= ((SEC_FLAG AND NOT CNT(0).LFBK)
	OR (NOT SEC_FLAG AND NOT DATA_FLAG AND CNT(0).LFBK));

FDCPE_CNT1: FDCPE port map (CNT(1),CNT_D(1),FX,'0','0');
CNT_D(1) <= ((SEG_7_OBUFE.EXP)
	OR (SEC_FLAG AND NOT CNT(0) AND CNT(1).LFBK));

FTCPE_CNT2: FTCPE port map (CNT(2),CNT_T(2),FX,'0','0');
CNT_T(2) <= ((SEC_FLAG AND CNT(0) AND CNT(1))
	OR (NOT SEC_FLAG AND DATA_FLAG AND CNT(2).LFBK));

FTCPE_CNT3: FTCPE port map (CNT(3),CNT_T(3),FX,'0','0');
CNT_T(3) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(3).LFBK)
	OR (SEC_FLAG AND CNT(1) AND CNT(2) AND CNT(0).LFBK)
	OR (SEC_FLAG AND NOT CNT(1) AND NOT CNT(2) AND CNT(0).LFBK AND 
	CNT(3).LFBK));

FTCPE_CNT4: FTCPE port map (CNT(4),CNT_T(4),FX,'0','0');
CNT_T(4) <= ((NOT SEC_FLAG AND DATA_FLAG.LFBK AND CNT(4).LFBK)
	OR (SEC_FLAG AND CNT(0) AND NOT CNT(2) AND CNT(3) AND 
	NOT CNT(1).LFBK));

FTCPE_CNT5: FTCPE port map (CNT(5),CNT_T(5),FX,'0','0');
CNT_T(5) <= ((CNT(7).EXP)
	OR (SEC_FLAG AND CNT(0) AND NOT CNT(2) AND CNT(3) AND 
	CNT(4).LFBK AND NOT CNT(1).LFBK AND CNT(6).LFBK)
	OR (SEC_FLAG AND CNT(0) AND NOT CNT(2) AND CNT(3) AND 
	CNT(4).LFBK AND NOT CNT(1).LFBK AND NOT CNT(7).LFBK));

FTCPE_CNT6: FTCPE port map (CNT(6),CNT_T(6),FX,'0','0');
CNT_T(6) <= ((NOT SEC_FLAG AND DATA_FLAG.LFBK AND CNT(6).LFBK)
	OR (SEC_FLAG AND CNT(0) AND NOT CNT(2) AND CNT(3) AND 
	CNT(4).LFBK AND NOT CNT(1).LFBK AND CNT(5).LFBK));

FTCPE_CNT7: FTCPE port map (CNT(7),CNT_T(7),FX,'0','0');
CNT_T(7) <= ((NOT SEC_FLAG AND DATA_FLAG.LFBK AND CNT(7).LFBK)
	OR (SEC_FLAG AND CNT(0) AND NOT CNT(2) AND CNT(3) AND 
	CNT(4).LFBK AND NOT CNT(1).LFBK AND CNT(6).LFBK AND CNT(5).LFBK)
	OR (SEC_FLAG AND CNT(0) AND NOT CNT(2) AND CNT(3) AND 
	CNT(4).LFBK AND NOT CNT(1).LFBK AND NOT CNT(6).LFBK AND CNT(7).LFBK AND 
	NOT CNT(5).LFBK));

FTCPE_CNT8: FTCPE port map (CNT(8),CNT_T(8),FX,'0','0');
CNT_T(8) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(8).LFBK)
	OR (SEC_FLAG AND CNT(4) AND NOT CNT(1) AND NOT CNT(2) AND NOT CNT(5) AND 
	NOT CNT(6) AND CNT(7) AND CNT(0).LFBK AND CNT(3).LFBK));

FTCPE_CNT9: FTCPE port map (CNT(9),CNT_T(9),FX,'0','0');
CNT_T(9) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(9).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND CNT(10).LFBK AND 
	NOT CNT(2).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(2).LFBK AND 
	CNT(9).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(2).LFBK AND 
	NOT CNT(11).LFBK));

FTCPE_CNT10: FTCPE port map (CNT(10),CNT_T(10),FX,'0','0');
CNT_T(10) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(10).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(2).LFBK AND 
	CNT(9).LFBK));

FTCPE_CNT11: FTCPE port map (CNT(11),CNT_T(11),FX,'0','0');
CNT_T(11) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(11).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND CNT(10).LFBK AND 
	NOT CNT(2).LFBK AND CNT(9).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(10).LFBK AND 
	NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK));

FTCPE_CNT12: FTCPE port map (CNT(12),CNT_T(12),FX,'0','0');
CNT_T(12) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(12).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(10).LFBK AND 
	NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK));

FTCPE_CNT13: FTCPE port map (CNT(13),CNT_T(13),FX,'0','0');
CNT_T(13) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(13).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(10).LFBK AND 
	NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND CNT(12).LFBK));

FTCPE_CNT14: FTCPE port map (CNT(14),CNT_T(14),FX,'0','0');
CNT_T(14) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(14).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(10).LFBK AND 
	NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND 
	CNT(13).LFBK));

FTCPE_CNT15: FTCPE port map (CNT(15),CNT_T(15),FX,'0','0');
CNT_T(15) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(15).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT CNT(10).LFBK AND 
	NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND CNT(12).LFBK AND 
	CNT(13).LFBK AND CNT(14).LFBK));

FTCPE_COUNTER0: FTCPE port map (COUNTER(0),'1',CLK,'0','0');

FTCPE_COUNTER1: FTCPE port map (COUNTER(1),COUNTER(0).LFBK,CLK,'0','0');

FTCPE_COUNTER2: FTCPE port map (COUNTER(2),COUNTER_T(2),CLK,'0','0');
COUNTER_T(2) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK);

FTCPE_COUNTER3: FTCPE port map (COUNTER(3),COUNTER_T(3),CLK,'0','0');
COUNTER_T(3) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK);

FTCPE_COUNTER4: FTCPE port map (COUNTER(4),COUNTER_T(4),CLK,'0','0');
COUNTER_T(4) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK);

FTCPE_COUNTER5: FTCPE port map (COUNTER(5),COUNTER_T(5),CLK,'0','0');
COUNTER_T(5) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK);

FTCPE_COUNTER6: FTCPE port map (COUNTER(6),COUNTER_T(6),CLK,'0','0');
COUNTER_T(6) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK);

FTCPE_COUNTER7: FTCPE port map (COUNTER(7),COUNTER_T(7),CLK,'0','0');
COUNTER_T(7) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK);

FTCPE_COUNTER8: FTCPE port map (COUNTER(8),COUNTER_T(8),CLK,'0','0');
COUNTER_T(8) <= (COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK);

FTCPE_COUNTER9: FTCPE port map (COUNTER(9),COUNTER_T(9),CLK,'0','0');
COUNTER_T(9) <= ((NOT COUNTER(0))
	OR (NOT COUNTER(1))
	OR (NOT COUNTER(2))
	OR (NOT COUNTER(3))
	OR (NOT COUNTER(4))
	OR (EXP5_.EXP)
	OR (Mmux_SEG_BUF_I4_Result_cmp_eq0001.EXP));

FTCPE_COUNTER10: FTCPE port map (COUNTER(10),COUNTER_T(10),CLK,'0','0');
COUNTER_T(10) <= ((COUNTER(0) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND COUNTER(24).LFBK));

FTCPE_COUNTER11: FTCPE port map (COUNTER(11),COUNTER_T(11),CLK,'0','0');
COUNTER_T(11) <= (COUNTER(10) AND COUNTER(9) AND COUNTER(0).LFBK AND 
	COUNTER(1).LFBK AND COUNTER(2).LFBK AND COUNTER(3).LFBK AND 
	COUNTER(4).LFBK AND COUNTER(5).LFBK AND COUNTER(6).LFBK AND 
	COUNTER(7).LFBK AND COUNTER(8).LFBK);

FTCPE_COUNTER12: FTCPE port map (COUNTER(12),COUNTER_T(12),CLK,'0','0');
COUNTER_T(12) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(1) AND 
	COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND 
	COUNTER(6) AND COUNTER(7) AND COUNTER(8) AND COUNTER(10).LFBK AND 
	COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER13: FTCPE port map (COUNTER(13),COUNTER_T(13),CLK,'0','0');
COUNTER_T(13) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(1) AND 
	COUNTER(2) AND COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND 
	COUNTER(6) AND COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND 
	COUNTER(10).LFBK AND COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER14: FTCPE port map (COUNTER(14),COUNTER_T(14),CLK,'0','0');
COUNTER_T(14) <= (COUNTER(12) AND COUNTER(10) AND COUNTER(13) AND 
	COUNTER(9) AND COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(11).LFBK);

FTCPE_COUNTER15: FTCPE port map (COUNTER(15),COUNTER_T(15),CLK,'0','0');
COUNTER_T(15) <= (COUNTER(12) AND COUNTER(10) AND COUNTER(13) AND 
	COUNTER(9) AND COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(11).LFBK AND COUNTER(14).LFBK);

FTCPE_COUNTER16: FTCPE port map (COUNTER(16),COUNTER_T(16),CLK,'0','0');
COUNTER_T(16) <= (COUNTER(12) AND COUNTER(10) AND COUNTER(13) AND 
	COUNTER(9) AND COUNTER(0).LFBK AND COUNTER(1).LFBK AND 
	COUNTER(2).LFBK AND COUNTER(3).LFBK AND COUNTER(4).LFBK AND 
	COUNTER(5).LFBK AND COUNTER(6).LFBK AND COUNTER(7).LFBK AND 
	COUNTER(8).LFBK AND COUNTER(11).LFBK AND COUNTER(14).LFBK AND 
	COUNTER(15).LFBK);

FTCPE_COUNTER17: FTCPE port map (COUNTER(17),COUNTER_T(17),CLK,'0','0');
COUNTER_T(17) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER18: FTCPE port map (COUNTER(18),COUNTER_T(18),CLK,'0','0');
COUNTER_T(18) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER19: FTCPE port map (COUNTER(19),COUNTER_T(19),CLK,'0','0');
COUNTER_T(19) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER20: FTCPE port map (COUNTER(20),COUNTER_T(20),CLK,'0','0');
COUNTER_T(20) <= (COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND COUNTER(9).LFBK);

FTCPE_COUNTER21: FTCPE port map (COUNTER(21),COUNTER_T(21),CLK,'0','0');
COUNTER_T(21) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND COUNTER(20).LFBK AND COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER22: FTCPE port map (COUNTER(22),COUNTER_T(22),CLK,'0','0');
COUNTER_T(22) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FTCPE_COUNTER23: FTCPE port map (COUNTER(23),COUNTER_T(23),CLK,'0','0');
COUNTER_T(23) <= (COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND COUNTER(9).LFBK);

FTCPE_COUNTER24: FTCPE port map (COUNTER(24),COUNTER_T(24),CLK,'0','0');
COUNTER_T(24) <= ((COUNTER(11) AND COUNTER(0) AND COUNTER(14) AND 
	COUNTER(15) AND COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND COUNTER(23).LFBK AND COUNTER(9).LFBK)
	OR (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK));

FDCPE_DATA_FLAG: FDCPE port map (DATA_FLAG,SEG_2_OBUFE.EXP,FX,'0','0');

FTCPE_DISP_CNT0: FTCPE port map (DISP_CNT(0),DISP_CNT_T(0),FX,'0','0');
DISP_CNT_T(0) <= ((NOT SEC_FLAG AND CNT(0) AND NOT DISP_CNT(0).LFBK AND 
	DATA_FLAG.LFBK)
	OR (NOT SEC_FLAG AND NOT CNT(0) AND DISP_CNT(0).LFBK AND 
	DATA_FLAG.LFBK));

FTCPE_DISP_CNT1: FTCPE port map (DISP_CNT(1),DISP_CNT_T(1),FX,'0','0');
DISP_CNT_T(1) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(1) AND 
	NOT DISP_CNT(1).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(1) AND 
	DISP_CNT(1).LFBK));

FTCPE_DISP_CNT2: FTCPE port map (DISP_CNT(2),DISP_CNT_T(2),FX,'0','0');
DISP_CNT_T(2) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(2) AND 
	NOT DISP_CNT(2).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(2) AND 
	DISP_CNT(2).LFBK));

FTCPE_DISP_CNT3: FTCPE port map (DISP_CNT(3),DISP_CNT_T(3),FX,'0','0');
DISP_CNT_T(3) <= ((NOT SEC_FLAG AND DATA_FLAG AND DISP_CNT(3).LFBK AND 
	NOT CNT(3).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT DISP_CNT(3).LFBK AND 
	CNT(3).LFBK));

FTCPE_DISP_CNT4: FTCPE port map (DISP_CNT(4),DISP_CNT_T(4),FX,'0','0');
DISP_CNT_T(4) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(4) AND 
	NOT DISP_CNT(4).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(4) AND 
	DISP_CNT(4).LFBK));

FTCPE_DISP_CNT5: FTCPE port map (DISP_CNT(5),DISP_CNT_T(5),FX,'0','0');
DISP_CNT_T(5) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(5) AND 
	NOT DISP_CNT(5).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(5) AND 
	DISP_CNT(5).LFBK));

FTCPE_DISP_CNT6: FTCPE port map (DISP_CNT(6),DISP_CNT_T(6),FX,'0','0');
DISP_CNT_T(6) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(6) AND 
	NOT DISP_CNT(6).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(6) AND 
	DISP_CNT(6).LFBK));

FTCPE_DISP_CNT7: FTCPE port map (DISP_CNT(7),DISP_CNT_T(7),FX,'0','0');
DISP_CNT_T(7) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(7) AND 
	NOT DISP_CNT(7).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(7) AND 
	DISP_CNT(7).LFBK));

FTCPE_DISP_CNT8: FTCPE port map (DISP_CNT(8),DISP_CNT_T(8),FX,'0','0');
DISP_CNT_T(8) <= ((NOT SEC_FLAG AND DATA_FLAG AND DISP_CNT(8).LFBK AND 
	NOT CNT(8).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT DISP_CNT(8).LFBK AND 
	CNT(8).LFBK));

FTCPE_DISP_CNT9: FTCPE port map (DISP_CNT(9),DISP_CNT_T(9),FX,'0','0');
DISP_CNT_T(9) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(9).LFBK AND 
	NOT DISP_CNT(9).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(9).LFBK AND 
	DISP_CNT(9).LFBK));

FTCPE_DISP_CNT10: FTCPE port map (DISP_CNT(10),DISP_CNT_T(10),FX,'0','0');
DISP_CNT_T(10) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(10).LFBK AND 
	NOT DISP_CNT(10).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(10).LFBK AND 
	DISP_CNT(10).LFBK));

FTCPE_DISP_CNT11: FTCPE port map (DISP_CNT(11),DISP_CNT_T(11),FX,'0','0');
DISP_CNT_T(11) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(11).LFBK AND 
	NOT DISP_CNT(11).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(11).LFBK AND 
	DISP_CNT(11).LFBK));

FTCPE_DISP_CNT12: FTCPE port map (DISP_CNT(12),DISP_CNT_T(12),FX,'0','0');
DISP_CNT_T(12) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(12).LFBK AND 
	NOT DISP_CNT(12).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(12).LFBK AND 
	DISP_CNT(12).LFBK));

FTCPE_DISP_CNT13: FTCPE port map (DISP_CNT(13),DISP_CNT_T(13),FX,'0','0');
DISP_CNT_T(13) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(13).LFBK AND 
	NOT DISP_CNT(13).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(13).LFBK AND 
	DISP_CNT(13).LFBK));

FTCPE_DISP_CNT14: FTCPE port map (DISP_CNT(14),DISP_CNT_T(14),FX,'0','0');
DISP_CNT_T(14) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(14).LFBK AND 
	NOT DISP_CNT(14).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(14).LFBK AND 
	DISP_CNT(14).LFBK));

FTCPE_DISP_CNT15: FTCPE port map (DISP_CNT(15),DISP_CNT_T(15),FX,'0','0');
DISP_CNT_T(15) <= ((NOT SEC_FLAG AND DATA_FLAG AND CNT(15).LFBK AND 
	NOT DISP_CNT(15).LFBK)
	OR (NOT SEC_FLAG AND DATA_FLAG AND NOT CNT(15).LFBK AND 
	DISP_CNT(15).LFBK));













FTCPE_OVER_FLAG: FTCPE port map (OVER_FLAG,OVER_FLAG_T,FX,'0','0');
OVER_FLAG_T <= ((EXP0_.EXP)
	OR (CNT(9).EXP)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND OVER_FLAG.LFBK AND 
	NOT CNT(10).LFBK AND NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND 
	NOT CNT(15).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND OVER_FLAG.LFBK AND 
	NOT CNT(10).LFBK AND NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND 
	CNT(12).LFBK AND CNT(13).LFBK AND CNT(14).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND OVER_FLAG.LFBK AND 
	NOT CNT(10).LFBK AND NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND 
	NOT CNT(12).LFBK AND NOT CNT(13).LFBK AND NOT CNT(14).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT OVER_FLAG.LFBK AND 
	NOT CNT(10).LFBK AND NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND 
	CNT(15).LFBK AND CNT(12).LFBK AND NOT CNT(13).LFBK)
	OR (SEC_FLAG AND CNT(0) AND CNT(4) AND CNT(8) AND NOT CNT(1) AND 
	NOT CNT(5) AND NOT CNT(6) AND CNT(3) AND CNT(7) AND NOT OVER_FLAG.LFBK AND 
	NOT CNT(10).LFBK AND NOT CNT(2).LFBK AND NOT CNT(9).LFBK AND CNT(11).LFBK AND 
	CNT(15).LFBK AND NOT CNT(12).LFBK AND CNT(13).LFBK));

FTCPE_SEC_FLAG: FTCPE port map (SEC_FLAG,SEC_FLAG_T,CLK,'0','0');
SEC_FLAG_T <= (NOT COUNTER(11) AND COUNTER(0) AND NOT COUNTER(14) AND 
	NOT COUNTER(15) AND NOT COUNTER(16) AND COUNTER(1) AND COUNTER(2) AND 
	COUNTER(3) AND COUNTER(4) AND COUNTER(5) AND COUNTER(6) AND 
	COUNTER(7) AND COUNTER(8) AND COUNTER(12).LFBK AND COUNTER(10).LFBK AND 
	COUNTER(13).LFBK AND COUNTER(17).LFBK AND COUNTER(18).LFBK AND 
	COUNTER(19).LFBK AND NOT COUNTER(20).LFBK AND COUNTER(21).LFBK AND 
	COUNTER(22).LFBK AND NOT COUNTER(23).LFBK AND NOT COUNTER(9).LFBK AND 
	COUNTER(24).LFBK);


SEG_I(0) <= NOT (((OVER_FLAG)
	OR (EXP2_.EXP)
	OR (COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND NOT DISP_CNT(9) AND NOT DISP_CNT(8).LFBK)
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND NOT DISP_CNT(9) AND DISP_CNT(8).LFBK)
	OR (NOT COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(0) AND 
	NOT DISP_CNT(1).LFBK AND NOT DISP_CNT(2).LFBK AND NOT DISP_CNT(3).LFBK)));
SEG(0) <= SEG_I(0) when SEG_OE(0) = '1' else 'Z';
SEG_OE(0) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT;


SEG_I(1) <= NOT (((OVER_FLAG)
	OR (EXP1_.EXP)
	OR (COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND DISP_CNT(9) AND NOT DISP_CNT(8).LFBK)
	OR (COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND NOT DISP_CNT(9) AND DISP_CNT(8).LFBK)
	OR (NOT COUNTER(12) AND NOT COUNTER(11) AND NOT DISP_CNT(0) AND 
	DISP_CNT(1).LFBK AND DISP_CNT(2).LFBK AND NOT DISP_CNT(3).LFBK)));
SEG(1) <= SEG_I(1) when SEG_OE(1) = '1' else 'Z';
SEG_OE(1) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT;


SEG_I(2) <= NOT (((OVER_FLAG)
	OR (SEG(5)_BUFR.EXP)
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND NOT DISP_CNT(8) AND DISP_CNT(9))
	OR (NOT COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(1) AND 
	NOT DISP_CNT(2) AND NOT DISP_CNT(3) AND NOT DISP_CNT(0).LFBK)));
SEG(2) <= SEG_I(2) when SEG_OE(2) = '1' else 'Z';
SEG_OE(2) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK;


SEG_I(3) <= NOT (((OVER_FLAG)
	OR (SEG_4_OBUFE.EXP)
	OR (DATA_FLAG.EXP)
	OR (COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND DISP_CNT(8) AND DISP_CNT(9))
	OR (COUNTER(12) AND NOT COUNTER(11) AND DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND NOT DISP_CNT(8) AND NOT DISP_CNT(9))
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND DISP_CNT(8) AND NOT DISP_CNT(9))));
SEG(3) <= SEG_I(3) when SEG_OE(3) = '1' else 'Z';
SEG_OE(3) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK;


SEG_I(4) <= EXP4_.EXP;
SEG(4) <= SEG_I(4) when SEG_OE(4) = '1' else 'Z';
SEG_OE(4) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK;


SEG_I(5) <= SEG(5)_BUFR.LFBK;
SEG(5) <= SEG_I(5) when SEG_OE(5) = '1' else 'Z';
SEG_OE(5) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK;


SEG(5)_BUFR <= NOT (((OVER_FLAG)
	OR (EXP3_.EXP)
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT DISP_CNT(10) AND 
	NOT DISP_CNT(11) AND DISP_CNT(8))
	OR (NOT COUNTER(12) AND NOT COUNTER(11) AND NOT DISP_CNT(2) AND 
	NOT DISP_CNT(3) AND DISP_CNT(0).LFBK)));


SEG_I(6) <= NOT (((CNT(1).EXP)
	OR (COUNTER(12) AND COUNTER(11) AND NOT OVER_FLAG AND 
	NOT DISP_CNT(13) AND NOT DISP_CNT(14) AND NOT DISP_CNT(15))
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT OVER_FLAG AND 
	NOT DISP_CNT(10) AND NOT DISP_CNT(11) AND NOT DISP_CNT(9))
	OR (NOT COUNTER(12) AND COUNTER(11) AND NOT OVER_FLAG AND 
	NOT DISP_CNT(5) AND NOT DISP_CNT(6) AND NOT DISP_CNT(7))
	OR (NOT COUNTER(12) AND NOT COUNTER(11) AND NOT OVER_FLAG AND 
	NOT DISP_CNT(1) AND NOT DISP_CNT(2) AND NOT DISP_CNT(3))));
SEG(6) <= SEG_I(6) when SEG_OE(6) = '1' else 'Z';
SEG_OE(6) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK;


SEG_I(7) <= '0';
SEG(7) <= SEG_I(7) when SEG_OE(7) = '1' else 'Z';
SEG_OE(7) <= NOT SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT.LFBK;


SEG_7_OBUFE/SEG_7_OBUFE_TRST__$INT <= ((CNT(5).EXP)
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT OVER_FLAG AND 
	DISP_CNT(10) AND DISP_CNT(11))
	OR (COUNTER(12) AND NOT COUNTER(11) AND NOT OVER_FLAG AND 
	DISP_CNT(11) AND DISP_CNT(9))
	OR (NOT COUNTER(12) AND COUNTER(11) AND NOT OVER_FLAG AND 
	DISP_CNT(5) AND DISP_CNT(7))
	OR (NOT COUNTER(12) AND COUNTER(11) AND NOT OVER_FLAG AND 
	DISP_CNT(6) AND DISP_CNT(7))
	OR (NOT COUNTER(12) AND NOT COUNTER(11) AND NOT OVER_FLAG AND 
	DISP_CNT(1) AND DISP_CNT(3)));


SEL(0) <= (NOT COUNTER(11) AND NOT COUNTER(12).LFBK);


SEL(1) <= (COUNTER(11) AND NOT COUNTER(12).LFBK);


SEL(2) <= (NOT COUNTER(11) AND COUNTER(12).LFBK);


SEL(3) <= DISP_CNT(0).EXP;

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-10-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-10-PC84                    65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              43 TIE                           
  2 TIE                              44 TIE                           
  3 TIE                              45 TIE                           
  4 TIE                              46 TIE                           
  5 TIE                              47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 CLK                              51 TIE                           
 10 FX                               52 TIE                           
 11 TIE                              53 TIE                           
 12 TIE                              54 SEL<0>                        
 13 TIE                              55 SEL<1>                        
 14 TIE                              56 SEL<2>                        
 15 TIE                              57 SEL<3>                        
 16 GND                              58 TIE                           
 17 TIE                              59 TDO                           
 18 TIE                              60 GND                           
 19 TIE                              61 TIE                           
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 SEG<7>                        
 24 TIE                              66 SEG<6>                        
 25 TIE                              67 SEG<5>                        
 26 TIE                              68 SEG<4>                        
 27 GND                              69 SEG<3>                        
 28 TDI                              70 SEG<2>                        
 29 TMS                              71 SEG<1>                        
 30 TCK                              72 SEG<0>                        
 31 TIE                              73 VCC                           
 32 TIE                              74 TIE                           
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 TIE                              79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 TIE                           
 40 TIE                              82 TIE                           
 41 TIE                              83 TIE                           
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-10-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25