Timing Report

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Design Name CLR_T_FF
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Sun May 02 07:43:28 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Clock Pulse Width for T
Clock to Setup (tCYC) 9.000 ns.
Clock Pad to Output Pad Delay (tCO) 10.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 9.0 1 1
AUTO_TS_P2P 0.0 10.0 2 2
AUTO_TS_P2F 0.0 6.5 2 2
AUTO_TS_F2P 0.0 3.5 2 2


Constraint: TS1000

Description: PERIOD:PERIOD_T:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q.Q to QB.D 0.000 9.000 -9.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
T to Q 0.000 10.000 -10.000
T to QB 0.000 10.000 -10.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
T to Q.CLKF 0.000 6.500 -6.500
T to QB.CLKF 0.000 6.500 -6.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q.Q to Q 0.000 3.500 -3.500
QB.Q to QB 0.000 3.500 -3.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
T 83.333 Limited by Clock Pulse Width for T

Setup/Hold Times for Clocks


Clock to Pad Timing

Clock T to Pad
Destination Pad Clock (edge) to Pad
Q 10.000
QB 10.000


Clock to Setup Times for Clocks

Clock to Setup for clock T
Source Destination Delay
Q.Q QB.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 7
Number of Timing errors: 7
Analysis Completed: Sun May 02 07:43:28 2010