********** Mapped Logic ********** |
FTCPE_Q0: FTCPE port map (Q(0),'1',CLK,NOT CLRB,'0'); |
FTCPE_Q1: FTCPE port map (Q(1),Q_T(1),CLK,NOT CLRB,'0');
Q_T(1) <= ((NOT Q_0.LFBK) OR (NOT Q_1.LFBK AND NOT Q_2.LFBK AND Q_3.LFBK)); |
FTCPE_Q2: FTCPE port map (Q(2),Q_T(2),CLK,NOT CLRB,'0');
Q_T(2) <= (Q_0.LFBK AND Q_1.LFBK); |
FTCPE_Q3: FTCPE port map (Q(3),Q_T(3),CLK,NOT CLRB,'0');
Q_T(3) <= ((Q_0.LFBK AND Q_1.LFBK AND Q_2.LFBK) OR (Q_0.LFBK AND NOT Q_1.LFBK AND NOT Q_2.LFBK AND Q_3.LFBK)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |