Timing Report

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Design Name CLR_SYT_FF
Device, Speed (SpeedFile Version) XC95108, -10 (3.0)
Date Created Sun May 02 07:48:49 2010
Created By Timing Report Generator: version J.30
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 9.000 ns.
Max. Clock Frequency (fSYSTEM) 111.111 MHz.
Limited by Clock Pulse Width for CLK
Clock to Setup (tCYC) 9.000 ns.
Setup to Clock at the Pad (tSU) 6.000 ns.
Clock Pad to Output Pad Delay (tCO) 6.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 9.0 1 1
AUTO_TS_P2P 0.0 6.0 2 2
AUTO_TS_P2F 0.0 8.5 3 3
AUTO_TS_F2P 0.0 3.5 2 2


Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q.Q to QB.D 0.000 9.000 -9.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to Q 0.000 6.000 -6.000
CLK to QB 0.000 6.000 -6.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
T to Q.D 0.000 8.500 -8.500
T to QB.D 0.000 8.500 -8.500
CLK to FCLKIO_0 0.000 2.500 -2.500


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Q.Q to Q 0.000 3.500 -3.500
QB.Q to QB 0.000 3.500 -3.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 111.111 Limited by Clock Pulse Width for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
T 6.000 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
Q 6.000
QB 6.000


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
Q.Q QB.D 9.000


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 8
Number of Timing errors: 8
Analysis Completed: Sun May 02 07:48:49 2010