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  OrCAD Programmable Logic Design Tools 386+ Version 2.00
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Enclosed is your OrCAD Programmable Logic Design Tools 386+
Version 2.00 product (PLD 386+).

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PLD 386+ V2.00 Features

PLD 386+ 2.00 is a major update to OrCAD's programmable logic solution. This
version contains significant enhancements in several key areas:
    - Vastly improved support for designing with OrCAD schematics.
         - Support for device independent multi-sheet flat or hierarchical
           schematics.
         - Automatic creation of OHDL source file from schematic. Simply
           create the schematic, netlist to OHDL source. Then compile, test,
           and fit as usual.
         - Automatic node insertion into schematic logic removes
           device-dependent design considerations.
         - Test vectors can be specified on schematic using pipe text.
    - Support for mixed schematic and HDL design methodology. OHDL can be
      included on the schematic sheets and will be transferred to the OHDL
      source file.
    - Advanced synthesis algorithms which allow creation of large multi-level
      structures.
    - One-hot state assignment. If sufficient state bits exist, PLD 386+ 2.00
      will automatically perform a one-hot state encoding.
    - Improved Windows compatibility. PLD 386+ 2.00 uses the PharLap extender
      to provide improved operation in a DOS Window under Windows 3.x.
    - Support for the latest programmable logic devices. PLD 386+ 2.00 now
      includes support for the latest devices as indicated below. All fitters
      that OrCAD currently provides are included with PLD 386+ 2.00.

The following devices are supported by PLD 386+ 2.00 OrCAD supplied fitters :

    -AMD      :  MACH 435
    -Cypress  :  CY7C258, CY7C259, CY7C330, CYC331, CYC332, CYC335
    -ICT      :  PEEL153, PEEL173, PEEL253, PEEL273
    -Intel    :  IFX740, IFX780, 5C180, 5AC312, 5AC324, 85C220, 85C224,
                 85C508, 85C22V10, 22V10
    -National :  MAPL128, MAPL144, MAPL244
    -Signetics:  CK2605, PLC18V8z
    -Toshiba  :  TC9800, TC9801

The following devices are targeted by PLD 386+ 2.00 (the fitter or layout software must be obtained from the
silicon vendor):

    -Actel FPGAs : Act1, Act2, Act3 series devices
    -Lattice     : pLSI/ispLSI: 1016, 1024, 1032, 1048
    -Xilinx FPGAs: 2K, 3K, 4K series
    -Xilinx EPLDs: XC7236, XC7236A, XC7272, XC73108

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Miscellaneous technical notes about PLD 386+ 2.00

1. AMD MACH 215 - Active low clock signals

To clock an output register the AMD MACH215 has the ability to use a clock
signal through a product term in the array, or from a clock pin (pin 13).
The clock signal can be defined as active high or active low.  A limitation
in the current version of the fitter (V1.67 7/24/92) is that it handles
only active high clock signals from pin 13.  If the clock signal needs to
be active low, assign it to a pin other than pin 13.  By assigning it to an
input or io pin other than pin 13, a product term will be utilized to clock
the register.  There are no problems with the clock product term being
declared active low.

The following design will create an incorrect JEDEC file:

   |MACH215 13:CLK, 14:IN, 15:OUT
   | Low:CLK
   | OUT = dff(IN, CLK)

Although this example does not define the clock as being active low it
produces the same incorrect results:

   |MACH215 13:CLK, 14:IN, 15:OUT
   |
   | OUT = dff(IN, CLK')


To remedy the situation assign the clock signal to another pin such as
pin 10:

   |MACH215 10:CLK, 14:IN, 15:OUT
   | Low:CLK
   | OUT = dff(IN, CLK)

Keep in mind that if the fitter is allowed to assign the pin numbers that
it may place the clock pin on pin 13.

A similar limitation exists with the clock on the MACH 230.


2. Intel micro-PLDs and EPLDs - Error message E8005 from DDBPINS program

E8005 may be generated by DDBPINS.EXE if you have targeted an Intel device
other than a FLEXlogic device.  This is an internal message that the software
adjusts to automatically.


3. Classic PALs - Asynchronous terms

If a design implements an asynchronous term, yet targets a PAL that does not
support one, the OrCAD fitter (DEVICE.EXE) will not report a problem.  The
designer should avoid implementing features that the device can not support.


4. MACH 435 - Placement is supplied by file option

To specify a file that contains the signal assignments of the last successful
fit use the <design>.old file, not the <design>.plc.


5. Xilinx XFPGA - Environment considerations

The Xilinx targeter software (SynthX/ImproveX) is not compatible with
MS-WINDOWS.


6. Xilinx XEPLD - PlusASM HDL

Fit Logic generates "stand-alone" PlusASM HDL files. To integrate these files
into a larger design structure each file must be edited to remove the PlusASM
PIN keywords.


7. Hardware function ff() - Invalid expressions

The flip-flop hardware function of OHDL, ff(), will not simulate correctly in
Test Logic.
Use the D-type or T-type flip-flop functions.


8. OrCAD SDT Release IV - FOHDLNET.EXE Netlist Formatter

PLD 386+ 2.00 does not support the netlist functionality of FOHDLNET.EXE in
OrCAD SDT Release IV software.  The original schematic entry design path is
still supported by using the PLDNET.CF or PLDNET.CCF netlist formatters.


9. OrCAD SDT 386+ Version 1.10 - Schematic pipe-text

SDT 386+ 1.10 (INET.EXE) ignores the second instance of pipe-text on a
schematic.

The following sample will cause INET.EXE to ignore the pipe-link command:

  |PLD
  |type: "MAPL244"
  |title: "Schematic Test"

       |LINK
       |PAGE2.SCH
       |PAGE3.SCH

To remedy the situation place an extra pipe character in the same column above
the original pipe-text.

  |PLD
  |type: "MAPL244"
  |title: "Schematic Test"

       |
       |LINK
       |PAGE2.SCH
       |PAGE3.SCH


10. Xilinx and Actel FPGAs

For a Xilinx or Actel design, the layout software from the respective silicon
vendor must be loaded before you can use PLD 386+ 2.00 to target those FPGAs.


11. Case sensitive signal names

To ensure proper pin placement annotation occurs between OrCAD PLD and third
party device fitters, be sure to capitalize all characters in the signal
names.  This is only an issue with the Intel and Lattice fitters, but in
general it is a good practice.


12. Lattice fitter

When fitting a Lattice device, if FitLogic reports "MSDOS Error #2:Path
or filename not found", either the Lattice fitter has not been installed
on your system, or it is not located in the DOS path.


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If improvements, bug fixes, or enhancements are available before the next
scheduled release of the product OrCAD Technical Support can make patches
available on the OrCAD BBS (503) 671-9401 or (503) 671-2050.


If you have any questions regarding this product, contact OrCAD Technical
Support at (503) 671-9400 (Monday-Friday, 6 AM to 4 PM pacific time).

Thanks for your support,  

OrCAD

