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     OrCAD Programmable Logic Design Tools 386+ Version 2.01
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Enclosed is your OrCAD Programmable Logic Design Tools 386+
Version 2.01 product (PLD 386+).

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PLD 386+ V2.01 Features

PLD 386+ 2.01 is a valuable update to OrCAD's programmable logic
solution. This version contains significant enhancements in
several key areas:

    - Logic compiler optimized to evaluate designs targeted at
      large PROM devices
    - Improved architecture specification technique
    - Improved PALASM output (Actel FPGAs or Xilinx XEPLDs)
    - New OrCAD PLD 386+ Vendor Support Application Notes for:
        Actel FPGAs
        AMD MACH 1 and MACH 2 devices
        Cypress EPLD and state machine PROMs
        Lattice pLSI and ispLSI devices
        National MAPL and MAPL2 FPLAs
	Xilinx EPLDs (XC7000) 2nd Revision
    - Various problem fixes

The following are new devices that can be targeted by PLD 386+ 2.01
(the fitter or layout software must be obtained from the silicon vendor):

    -Lattice     : pLSI/ispLSI: 1048c, 2032, and 3256


The remainder of this note describes the enhancements in detail.

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Miscellaneous technical notes about PLD 386+ 2.01

1. PROM designs - HEX file generation

If a PROM device is targeted, the logic compiler will no longer
attempt to optimize the logic functions defined in the OHDL source.
Since a PROM can store a separate output value for each combination
of inputs, it can store any logic function. The Compile Source
processor writes the (.hex) programming file after it evaluates the
(.pld) source. It is not necessary to run the Fit Logic processor.

2. Improved architecture specification technique - DEVTAB.TXT

How to target an architecture.
  To generate the proper logic interchange file, identify the
  device architecture in your OHDL source file. You can specify
  the silicon vendor, part value, and package to ensure that
  the PLD 386+ processors implement your design into the proper
  device. Syntax:
    |"vendor partvalue package-pincount" or
    |Type: "vendor partvalue package-pincount"

  If you are composing OHDL in a text editor, the sample source
  lines below demonstrate how to target a device.

    |"22V10 PLCC-28"
    |"Altera EP1830 PGA-68"
    |"Lattice is/pLSI1048 PLCC-120"


2. Improved architecture specification technique - DEVTAB.TXT (cont.)

  If you are using the schematic capture technique, use the
  PLACE Text command in Edit Schematic Logic, then use the type
  keywords as below:
  
    |Type: "AMD/MMI MACH435 PLCC-84"
    |Type: "Xilinx XC7272-30 JLCC-84"

  To view a complete list of device architectures supported by
  PLD 386+ 2.01, use View Reference Material to view DEVLIST.TXT.

3. Improved PALASM output - Actel FPGAs or Xilinx EPLDs

If you target a device that generates a (.pds) PALASM-syntax HDL
file, the Fit Logic processor will now report explicit pin and node
assignments made in the OHDL source. If signals are forced "high"
and "low" in the OHDL source, the signals will be assigned to VCC
and GND, respectively.

4. New OrCAD PLD 386+ Vendor Support Application Notes

A new application note for Cypress EPLDs and State Machine PROMs is
included in this update. If you would like to target Actel, AMD
MACH 1x2x, Lattice, National, or Xilinx XEPLD devices (2nd Revision),
fax your request for Vendor Support Application Notes to OrCAD
Technical Support at 503/671-9501. To view a complete list of device
architectures supported by PLD 386+ 2.01, use View Reference Material
to view DEVLIST.TXT.

5. Xilinx XACT 5.0 compatibility - Xilinx Fitter Kit 

The Xilinx Fitter Kit provided with PLD 386+ 2.0 and 2.01 is
compatible with Xilinx XACT 4.x product. If you need (.xnf) Xilinx
netlist modules that are compatible with XACT 5.x, contact OrCAD
Technical Support for an updated version of the Xilinx Fitter Kit.

6. National PLD Product Line Discontinued - National Fitter Kit

National has announced that its line of PLD products has been
discontinued. This includes the MAPL devices supported by the PLD 386+
National Fitter Kit. Check for device availability before implementing
any designs.

7. Altera acquires Intel PLD Line - Intel Fitter Kit

The Intel Fitter Kit includes device support for the Intel FLEXlogic
family, high performance micro-PLDs, and EPLDs. The JEDEC files generated
by the fitter kit are compatible with the Altera devices.

8. Fit Logic Filter Errors - AMD MACH 1x2x
If Fit Logic reports:
"Error: Unable to complete update to .LST and .VEC files." and
"MS DOS #6 Unknown. Refer to latest List of DOS Critical Error Handler codes",
an error file, JOB.ERR, will be generated. Error messages are reported
in JOB.ERR.


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Known Problems in PLD 386+ 2.01

1. Combinatorial Feedback with Combinatorial Output - PEEL devices

Problem:
The logic compiler does not implement combinatorial feedback with
combinatorial output in PEEL devices correctly; instead the feedback
path will originate from the pin. The sample source below illustrates
an example:

|PEEL18CV8 in: (A,B,OE), io: (P,Y), nodes: N
|N = A # B
|P = OE ?? N
|Y = N

Workaround:
None

2. Buried Product Terms with Schematic Entry - Classic PALs, and CPLDs

Problem:
The logic compiler does not bury registered product terms properly
if the design is captured as a schematic.

Workaround:
Manually pair the node with the pin.
   2a. Attach a module port to the buried PT on the schematic.
   2b. Declare the node as pipe-PLD text on the schematic.
       Sample: |PLD
               |nodes: (BURIED_PT/PIN_SIGNAL)
               |type: "PAL22V10"
For more information on output pairing, see the AMD MACH 1 and 2 Family
Application Note.

3. AMD MACH 215 - Active low clock signals

To clock an output register the AMD MACH215 has the ability to use a clock
signal through a product term in the array, or from a clock pin (pin 13).
The clock signal can be defined as active high or active low.  A limitation
in the current version of the fitter (V1.67 7/24/92) is that it handles
only active high clock signals from pin 13.  If the clock signal needs to
be active low, assign it to a pin other than pin 13.  By assigning it to an
input or io pin other than pin 13, a product term will be utilized to clock
the register.  There are no problems with the clock product term being
declared active low.

The following design will create an incorrect JEDEC file:

   |MACH215 13:CLK, 14:IN, 15:OUT
   | Low:CLK
   | OUT = dff(IN, CLK)


3. AMD MACH 215 - Active low clock signals (cont.)

Although this example does not define the clock as being active low it
produces the same incorrect results:

   |MACH215 13:CLK, 14:IN, 15:OUT
   |
   | OUT = dff(IN, CLK')


To remedy the situation assign the clock signal to another pin such as
pin 10:

   |MACH215 10:CLK, 14:IN, 15:OUT
   | Low:CLK
   | OUT = dff(IN, CLK)

Keep in mind that if the fitter is allowed to assign the pin numbers that
it may place the clock pin on pin 13.

A similar limitation exists with the clock on the MACH 230.


4. Intel micro-PLDs and EPLDs - Error message E8005 from DDBPINS program

E8005 may be generated by DDBPINS.EXE if you have targeted an Intel device
other than a FLEXlogic device.  This is an internal message that the software
adjusts to automatically.

5. MACH 435 - Placement is supplied by file option

To specify a file that contains the signal assignments of the last successful
fit use the <design>.old file, not the <design>.plc.


6. Xilinx Fitter Kit for XACT 4.x - Environment considerations

The Xilinx targeter software (SynthX/ImproveX) is not compatible with
MS-WINDOWS; however, the XACT 5.x version is.

7. OrCAD SDT Release IV - FOHDLNET.EXE Netlist Formatter

PLD 386+ 2.01 does not support the netlist functionality of FOHDLNET.EXE in
OrCAD SDT Release IV software.  The original schematic entry design path is
still supported by using the PLDNET.CF or PLDNET.CCF netlist formatters.

8. Case sensitive signal names

To ensure proper pin placement annotation occurs between OrCAD PLD and third
party device fitters, be sure to capitalize all characters in the signal
names.  This is only an issue with the Intel and Lattice fitters, but in
general it is a good practice.

9. Compile Source - Memory protection fault

If LOGIC.EXE encounters a signal identity ambiguity it may abort and report:
"Abnormal program termination: Memory protection fault." OHDL designs should
avoid index notation that introduces ambiguities. The sample source below
illustrates this idea.

|X1[11] = A
|X111   = B
|X11[1] = C
|A = B

Modify the code above to remove the numeric signal names.

|XA[11]  = A
|XB[111] = B
|XC[1]   = C
|A = B

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If improvements, bug fixes, or enhancements are available before
the next scheduled release of the product OrCAD Technical Support
can make patches available on the OrCAD BBS (503) 671-9401 or
(503) 671-2050.


If you have any questions regarding this product, contact OrCAD
Technical Support at (503) 671-9400 (Monday-Friday, 6 AM to 4 PM
pacific time).

Thanks for your support,  

OrCAD


